在通訊十分發達的如今，Radio Frequency(RF)射頻收發機已變成舉足輕重的角色，其中射頻收發機的內部構成便成為科技發展的主要方向，例如：低噪聲放大器(LNA)、頻率合成器(FS)、功率放大器 (PA)和混頻器(Mixer)。而此篇論文會主要著墨在頻率合成器(FS)，並提供三種低功率、低相位雜訊與寬鎖定範圍和震盪器特性的倍頻器之設計。
第一部分設計一個於閘極使用負偏壓的MOSFET倍頻器(二倍頻)，強制使倍頻器MOSFET的偏壓處於夾止（pinched-off）的狀態，以此達成降低直流所產生的功耗。閘級的負偏壓Class-D VCO內部電壓經由HBT整流器所產生。VCO亦提供三倍電源電壓峰值的電壓擺幅與高負電壓。此VCO-FD在tsmc 0.18 μm BiCMOS製程中，所使用的矽晶片面積為 1.1945 × 1.152 mm2。而此VCO可以藉由調整交叉耦合的FETs閘極偏壓來使倍頻的輸出頻率改變，其工作頻率為4.17 GHz至4.34 GHz。
第二部分設計一種使用tsmc 0.18 μm BiCMOS製程的單級LC-tank注入鎖定頻率六倍頻器(ILFS)，而ILFS由多個子電路與一個共用電源所組成。ILO的自振頻率位於5.617 GHz，在直流功耗20.9 mW與注入訊號功率0 dBm的情況下，×6輸入鎖定頻率為0.94 GHz至1.02 GHz，並提供輸出信號頻率範圍為5.64 GHz至6.12 GHz。此設計所使用的矽晶片面積為1.141 × 1.2 mm2。其他倍數之輸出頻率亦可在此設計上量測。
最後的部分設計一種新工作原理的注入鎖定倍頻器(×2n ILFM)，此倍頻器的電路基於一個注入鎖定震盪器(ILO)與nMOS倍頻器。ILO的自振頻率為2.93 GHz。在直流功耗20.9 mW與注入信號功率0 dBm的條件下，×2輸出鎖定範圍為 4.1 GHz 至 8.6 GHz 頻率。此晶片使用0.18 μm CMOS製程，其使用面積為1.141×1.2 mm2。ILFD電路具有較寬的鎖定範圍和良好的Phase noise。

Nowadays, Radio Frequency (RF) transceivers have become a pivotal role in the development of communications. The internal components of RF transceivers have become the main direction of technological development, such as Low Noise Amplifier (LNA), Frequency Synthesizer (FS), Power Amplifier (PA) and Mixer (Mixer). This thesis will focus on frequency synthesizer (FS) and provide three designs of frequency multiplier with low power consumption, low phase noise and wide locking range.
The first part designs a MOSFET frequency doubler (×2 FD) with negative gate bias to enforce the doubler MOSFET biased in the pinched-off to lower DC power dissipation. The negative gate bias is generated by the HBT diode rectifier using the class-D VCO internal voltages as input voltages. The integrated VCO-FD in the tsmc 0.18 μm BiCMOS uses a silicon die area of 1.1945×1.152 mm2. The varactor-less VCO is tunable by varying the gate bias of the capacitive cross-coupled FETs, so that the frequency doubler output frequency is tunable and it operates from 4.17 GHz to 4.34 GHz.
The second part designs a single-stage LC-tank injection locked frequency sixtupler (ILFS) fabricated in 0.18 μm CMOS process and the ILFS merges many sub-circuits in one by sharing a common supply and passive inductive elements. The differential input and single-phase output ILFS circuit is made of two frequency doublers, a first-harmonic injection-locked oscillator and an active frequency tripler using one frequency doubler. The free-running oscillation frequency of the ILO is around 5.716 GHz. At the DC power consumption of 20.9 mW and at the incident power of 0 dBm, the ×6 input locking range is from the incident frequency 0.94 GHz to 1.02 GHz to provide an output signal source from the frequency 5.64 GHz to 6.12 GHz. The whole chip occupies a die area of 1.141×1.2 mm2. Other high multiplier factors are also measured on the designed chip.
In the last part design, an injection locked frequency multiplier (×2n ILFM) with new operation principle is proposed and characterized. The circuit as a frequency doubler is based on one injection-locked oscillator (ILO) and an nMOS frequency doubler. The free-running oscillator frequency of the ILO is around 2.93 GHz. At the DC power consumption of 20.9 mW and at the incident power of 0 dBm, the ×2 output locking range is from the frequency 4.1 GHz to 8.6 GHz. The whole 0.18 μm CMOS chip occupies a silicon die area of 1.141×1.2 mm2. The ILFD circuit shows wide locking range and a good locked phase noise. The circuit is also used a single-stage LC-tank injection locked frequency quadrupler (ILFQ), the free-running oscillator frequency of the ILFQ is around 5.73 GHz. At the incident power of 0 dBm, the ×4 output locking range is from the frequency 5.55 GHz to 6.39 GHz.

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