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研究生: 侯岳廷
Yueh-Ting Hou
論文名稱: Alternative Encoding: A Two-step Transition Reduction Scheme for MLC STT-RAM
Alternative Encoding: A Two-step Transition Reduction Scheme for MLC STT-RAM
指導教授: 謝仁偉
Jen-Wei Hsieh
口試委員: 黃元欣
Yuan-Shin Hwang
劉一宇
Yi-Yu Liu
學位類別: 碩士
Master
系所名稱: 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 英文
論文頁數: 41
中文關鍵詞: MLC STT-RAMEncodingLifetime
外文關鍵詞: MLC STT-RAM, Encoding, Lifetime
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  • In recent years, spin-transfer torque random access memory (STT-RAM)
    has been considered as a potential candidate to replace SRAM in
    cache design. Compared with SRAM, STT-RAM has advantages of high
    data density, nearly zero leakage power, and non-volatility. In
    order to further increase data density, multi-level-cell (MLC)
    STT-RAM has been proposed. However, write disturbance of MLC STT-RAM
    incurs the two-step transition (TT) problem. The TT problem is
    resulted from its hard domain and soft domain cannot be flipped to
    the opposite magnetization direction at the same time. Therefore,
    the soft domain has to be flipped twice to flip to the opposite
    magnetization direction of the hard domain. The TT problem will hurt
    the lifetime of MLC STT-RAM due to the redundant flips on soft
    domains. In order to mitigate the TT problem of MLC STT-RAM, we
    propose an alternative encoding scheme (AES) to reduce the
    occurances of TTs. AES utilizes the encoding method to eliminate
    most TTs and takes a balance distribution of unavoidable TTs among
    cells to improve the lifetime of MLC STT-RAM. The experiment results
    showed that the proposed scheme achieved a great lifetime
    improvement than conventional MLC STT-RAM scheme and the related
    work.


    In recent years, spin-transfer torque random access memory (STT-RAM)
    has been considered as a potential candidate to replace SRAM in
    cache design. Compared with SRAM, STT-RAM has advantages of high
    data density, nearly zero leakage power, and non-volatility. In
    order to further increase data density, multi-level-cell (MLC)
    STT-RAM has been proposed. However, write disturbance of MLC STT-RAM
    incurs the two-step transition (TT) problem. The TT problem is
    resulted from its hard domain and soft domain cannot be flipped to
    the opposite magnetization direction at the same time. Therefore,
    the soft domain has to be flipped twice to flip to the opposite
    magnetization direction of the hard domain. The TT problem will hurt
    the lifetime of MLC STT-RAM due to the redundant flips on soft
    domains. In order to mitigate the TT problem of MLC STT-RAM, we
    propose an alternative encoding scheme (AES) to reduce the
    occurances of TTs. AES utilizes the encoding method to eliminate
    most TTs and takes a balance distribution of unavoidable TTs among
    cells to improve the lifetime of MLC STT-RAM. The experiment results
    showed that the proposed scheme achieved a great lifetime
    improvement than conventional MLC STT-RAM scheme and the related
    work.

    Contents 1 Introduction 5 2 Background 7 2.1 SLC STT-RAM and MLC STT-RAM . . . . . . . . . . . . . . 7 2.2 Write and Read Operations of MLC STT-RAM . . . . . . . . 8 2.3 Limited Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 Cache Architecture . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Related Work and Motivation 13 4 AES: Alternative Encoding Scheme 15 4.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 AES MLC STT-RAM Design . . . . . . . . . . . . . . . . . . 15 4.2.1 Assistant Cell and Segment . . . . . . . . . . . . . . . 16 4.2.2 Decision Table . . . . . . . . . . . . . . . . . . . . . . 16 4.2.3 Write Process of AES . . . . . . . . . . . . . . . . . . . 18 4.3 Wear Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 Illustrative Example . . . . . . . . . . . . . . . . . . . . . . . 20 5 Performance Evaluation 22 5.1 Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 Impacts of Di erent Threshold for AES . . . . . . . . . . . . . 24 5.3 Lifetime Evaluation . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 Write Distribution among Cells . . . . . . . . . . . . . . . . . 26 5.5 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . 26 5.6 Energy Evaluation . . . . . . . . . . . . . . . . . . . . . . . . 27 6 Conclusion 29

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