研究生: |
沈毓翔 Yu-Siang Shen |
---|---|
論文名稱: |
射頻模組失真補償的實現 Implementation of distortion compensation for RF modules |
指導教授: |
王煥宗
Huan-Chun Wang |
口試委員: |
王煥宗
Huan-Chun Wang 方文賢 Wen-Hsien Fang 曾德峰 Der-Feng Tseng 劉馨勤 Hsin-Chin Liu 林敬舜 Ching-Shun Lin |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2019 |
畢業學年度: | 107 |
語文別: | 中文 |
論文頁數: | 47 |
中文關鍵詞: | 星座圖 、誤差向量幅度 、增益失真 、IQ不平衡 、非線性失真 |
外文關鍵詞: | constellation, EVM, gain distortion, IQ imbalance, nonlinear distortion |
相關次數: | 點閱:257 下載:0 |
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本論文主要目的為透過觀察星座圖及EVM量測,設計演算法補償訊號失真,使EVM值達到規範要求,使用的系統是基於IEEE802.11a/g網路通訊協定與正交分頻多工調變(Orthogonal Frequency-Division Multiplexing, OFDM)系統的WARP V3 Reference Design,前人整合了新的RF模組AD9361來擴充傳送與接收的頻率與頻寬,但經由測試發現新的RF模組在中心頻率1GHz訊號頻寬2Mz時收發上封包的錯誤率高上許多,我們藉由觀察及分析星座圖和EVM值,來了解訊號傳送間產生的錯誤資訊,如:增益失真、非線性失真、IQ不平衡等。
找到改善通訊品質方向後,我們在WARP V3 Reference Design中增加原本設計中沒有的演算法,主要演算法為均方根增益失真補償,最後將實作的硬體電路燒入FPGA版來測試傳輸時的吞吐量及錯誤率,以及測試EVM品質是否達到標準。
The main purpose of this thesis is to design the algorithm to compensate for signal distortion by observing the constellation diagram and EVM measurement, so that the EVM value meets the specification requirements. The system used in this thesis is WARP V3 Reference Design based on IEEE802.11a/g network protocol and OFDM (Orthogonal Frequency-Division Multiplexing, OFDM). The predecessor integrates the new RF module AD9361 to expand the frequency and bandwidth of transmission and reception. By the experiment, we find out that the packet error rate of the new RF module is higher than when the center frequency is 1GHz and signal bandwidth is 2MHz. By observing and analyzing the constellation and the EVM, we understand the error information which generated by the signal transmission like gain distortion, nonlinear distortion, IQ imbalance, etc.
After finding out the way to improve communication quality, we add the algorithm in WARP V3 Reference Design which was not in the original design. The main function of the algorithm is root mean square (RMS) gain distortion compensation. Finally, the implemented hardware circuit is programed into the FPGA to test the throughput and error rate during transmission, and to test whether the EVM quality meets the specification.
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model”, May 2011
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