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研究生: 李文傑
WEN-JIE LI
論文名稱: 基於FPGA之深度卷積神經網路之高能效威諾格拉德一維最小化濾波器演算法
Energy-Efficient One-Dimension Winograd’s Minimal Filter Algorithm for Deep Convolutional Neural Networks based on FPGA
指導教授: 阮聖彰
Shanq-Jang Ruan
口試委員: 阮聖彰
Shanq-Jang Ruan
林昌鴻
Chang Hong Lin
林淵翔
Yuan-Hsiang Lin
劉一宇
Yi-Yu Liu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 英文
論文頁數: 41
中文關鍵詞: 卷積神經網路硬體加速器空間架構行固定資料流威諾格拉德演算法現場可程式邏輯閘陣列
外文關鍵詞: Convolutional Neural Networks, Hardware Accelerator, Spatial Architecture, Row Stationary Dataflow, Winograd’s Algorithm, FPGA
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  • 近期,最先進的卷積神經網路 (CNNs) 已經被廣泛應用於許多深度神經網路 (DNNs) 的模型。隨著深度神經網路的模型變得越來越準確,神經網路的計算量與需求的資料頻寬也明顯增加。我們針對以上問題,實現基於現場可程式邏輯閘陣列之卷積神經網路之硬體加速器。在本篇論文中,我們提出一種基於行固定資料流且具有空間特性的晶片網路架構 (NoCs),並使用快速卷積演算法,同時減少乘法計算量與資料頻寬。經過實驗結果指出,在批量大小為三的 VGG-16 卷積神經網路模型下,本論文所提出的設計與其他相關研究相比,總計算量能降低1.497倍,內部記憶體降低1.07倍的資料頻寬,並且外部記憶體降低1.46倍的資料頻寬。


    The state-of-the-art convolutional neural networks (CNNs) have been widely applied to many deep neural networks (DNNs) models. As the model becomes more accurate, both the number of computation and the data bandwidth are significantly increased. This paper presents the design and implementation of CNN accelerator based on FPGA. The proposed design uses the row stationary with the NoC and the fast convolution algorithm in process elements to reduce the number of computation and data bandwidth simultaneously. The experimental result which using the CNN layers of VGG-16 with a batch size of three shows that the proposed design is more energy efficient than the state-of-the-art work. The proposed design improves the total GOPs of the algorithm by 1.50 times and reduces the on-chip memory and off-chip memory bandwidth by 1.07 and 1.46 times than prior work respectively.

    摘 要 ABSTRACT ACKNOWLEDGEMENTS TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES LIST OF ALGORITHMS CHAPTER 1 INTRODUCTION 1.1 Introduction of Deep Neural Networks 1.2 Challenges of Existing Works 1.3 Contributions 1.4 Organization of This Thesis CHAPTER 2 BACKGROUND 2.1 Convolutional Neural Networks CHAPTER 3 RELATED WORKS 3.1 Data Quantization 3.2 Winograd’s Algorithm 3.3 Dataflow Topology CHAPTER 4 ARCHITECTURE 4.1 Overview 4.2 Processing Element and Algorithm 4.3 Network on Chip and Dataflow CHAPTER 5 EXPERIMENTAL RESULTS 5.1 Resource Usage 5.2 Performance Evaluation CHAPTER 6 CONCLUSION REFERENCE

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