動態隨機存取記憶體 (Dynamic Random Access Memory, DRAM) 中細胞 (Cell) 資料暫存時間 (Data Retention Time) 主宰著整個記憶體的刷新 (Refresh) 功率消耗及良率 (Yield)。目前的技術通過延長刷新週期來降低刷新功率消耗，但延長刷新週期會造成細胞發生資料保留錯誤 (Data Retention Fault)，因此相關技術提出修正或避免此種錯誤發生的方法，像是採用錯誤偵測與修正碼 (Error Detection and Correction) 來修正資料保留錯誤，但需要額外的硬體成本及喪失對暫態錯誤 (Transient Fault) 的保護能力；或是依照實體區域分配刷新週期，但各區域的刷新週期會受到其中最短資料暫存時間的細胞所控制。
本論文中提出適應性 (Adaptive) 區塊調整刷新技術，透過適應性的延長記憶體刷新週期的方式來降低刷新功率消耗，進而降低因延長刷新週期所產生的資料保留錯誤細胞的數目，會透過映射的方式集中至特定區域。當記憶體在刷新細胞時，只需配置所需求的刷新週期至特定區域即可，而其他區域則可使用延長後的刷新週期，另外若特定區域內細胞資料暫存時間較短於硬體提供的刷新週期，本技術可以提供更短的刷新週期給特定區域，使記憶體的良率提升。本技術相較其他技術，能分配更貼近細胞的刷新週期，所以可以降低更多的刷新功率，並提升記憶體良率，且不需花費大量的硬體成本。
本技術最後的結果顯示，1Gb的記憶體在細胞的資料暫存時間分布為常態分布時，只需付出不到1% 的硬體成本，而且子記憶體站位址重映射技術最多可以節省74.97% 的刷新功率消耗，透過內容定址記憶體重映射技術則最多可節省86.67% 的刷新功率消耗。良率提升表現則與硬體提供的最短刷新週期有關，當標準刷新週期由64 ms降低至32 ms、16 ms及8 ms時，良率分別可以提升0.68倍、0.96倍和1.09倍。

For dynamic random access memory (DRAM), data retention time of DRAM cells dominate the refresh power consumption and fabrication yield. Although extending the standard refresh period is one of the most widely used method for reducing refresh power, however, it will inevitably cause further data retention faults. Recently, there are many techniques proposed for repairing or avoidance of these faults. For example, error detection and correction codes (EDAC) can be used to correct data retention faults. However, EDAC requires extra hardware cost for implementing the encoding/decoding circuits. Besides, it also sacrifices the protection ability for transient faults. Other techniques try to logically partition the DRAM address space into spatially disjoint regions. Thereafter, a suitable refresh period is allocated for each region. The main drawback is that the refresh period is limited by the cell with the shortest data retention time in each region.
In this thesis, two adaptive block-based refresh techniques for reducing DRAM refresh power and mitigation of data retention faults are proposed. For the first technique, we develop a control word remapping approach. We partition a memory bank into spatially disjoint sub-banks. A sub-bank can recover a row which includes data retention faults. We remap this row to the bottom of this sub-bank by the associated control word and allocate a suitable refresh period for it. Alternately, the other rows in the same sub-bank can use an extended refresh period. The second technique is an address remapping approach. We define a cluster region formed by remapping the rows which include data retention faults. We reconfigure the mapping between the physical address and logical address to achieve this goal. Then, we provide the required refresh periods for these rows to mitigate their faults. Thereafter, the rows which do not belong to the cluster region can use an extended refresh period. These two techniques reduce the number of rows which should be refreshed too often. Besides, the rows which contain data retention faults still can be refreshed adequately.
Experimental results show that sub-bank address remapping technique can save 74.97% refresh power and CAM-based address remapping technique also can save 86.67% refresh power with less than 1% hardware overhead for a 1-Gb DRAM. In our simulation, we assume that the data retention time follows the normal distribution. If we decrease the standard refresh period from 64 ms to 32 ms, 16 ms, and 8 ms; the yield can be improved 0.68, 0.96, and 1.09 times, respectively.

[1]http://www.itrs2.net/2011-itrs.html
[2]Y.-C. Yu, C.-S. Hou, L.-J. Chang, J.-F. Li, C.-Y. Lo, D. Kwai, and C.-W. Wu, “A hybrid ECC and redundancy technique for reducing refresh power of DRAMS,” in Proc. VLSI Test Symp. (VTS), pp. 1–6, Apr. 2013.
[3]C. Wilkerson, A. R. Alameldeen, Z. Chishti, W. Wu, D. Somasekhar, and S.-L. Lu, “Reducing cache power with low-cost, multi-bit error-correcting codes,” in Proc. 2010 ACM/IEEE 37st Int. Symp. on Computer Architecture (ISCA), pp. 175–186, Jun. 2010.
[4]J. Kim and M. C. Papaefthymiou, “Block-based multiperiod dynamic memory design for low data-retention power,” IEEE Trans. on VLSI Systems, vol. 11, no. 6, pp. 1006–1018, Dec. 2003.
[5]A. Agrawal, A. Ansari, and J. Torrellas, “Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules,” in Proc. of the 20th Int. Symp. on High-Performance Computer Architecture (HPCA’14), pp. 84–95, 2014.
[6]J. Li, B. Jaiyen, R. Veras, and O. Mutlu, “RAIDR: Retention-aware intelligent DRAM refresh,” in Proc. 39th Annual Int. Symp. on Computer Architecture (ISCA), pp. 1–12, 2012.
[7]T. Hamamoto, S. Sugiura, and S. Sawada “On the retention time distribution of dynamic random access memory (DRAM),” IEEE Trans. on Electron Devices, vol. 45, no. 6, pp. 1300–1309, June 1998.
[8]P. G. Emma, W. R. Reohr, and M. Meterelliyoz, “Rethinking refresh: increasing availability and reducing power in DRAM for cache applications” IEEE Micro, vol. 28, no. 6, pp. 47–56, Nov. 2008.
[9]S. Baek, S. Cho, and R. Melhem, “Refresh now and then,” IEEE Trans. on Computers, vol. 63, no. 12, pp. 3114–3126, Dec. 2014.
[10]D. W. Kim and M. Erez, “Balancing reliability, cost, and performance tradeoffs with FreeFault,” in Proc. of the 21th Int. Symp. on High-Performance Computer Architecture (HPCA’15), pp. 439–450, 2015.
[11]Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu, “Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors,” in Proc. 2014 ACM/IEEE 41st Int. Symp. on Computer Architecture (ISCA), pp. 361–372, June 2014.
[12]J.-F. Li and C.-M Chang, “BIST-assisted refresh power reduction techniques for DRAMs,” Department of Electrical Engineering National Central University, Jhongli, Taiwan, 2014.
[13]M. L. Bushnell and V. D. Agrawal, “Essentials of electronic testing for digital, memory and mixed-signal VLSI Circuits,” Kluwer Academic Publishers, 2000.
[14]J. van de Goor and Zai Al-Ars, “Functional memory faults: A formal notation and a taxonomy,” in Proc. IEEE VLSI Test Symp., pp. 281–289, Apr. 2000.
[15]C.-T. Huang, J.-R. Huang, C.-E Wu, C.-W. Wu, and T.-Y. Chang, “A programmable BIST core for embedded DRAM,” IEEE Design & Test of Computers, vol. 16, no. 1, pp. 59–70, Jan.–Mar. 1999.
[16]R. Nair, S. M. Thatte, and J. A. Abraham, ”Efficient algorithms for testing SRAMs,” IEEE Trans. on Computers, vol. C-27, no. 6, pp. 572–576, June 1978.
[17]R. Dekker, F. Bennker, and L. Thijssen, “Fault modeling and test algorithm development for static random access memories,” in Proc. Int. Test Conf., pp. 343–352, Sep. 1988.
[18]A. J. Van De Goor, “Using march tests to test SRAMs,” IEEE Design & Test of Computers, vol. 10, no. 1, pp. 8–14, Mar. 1993.
[19]Syntest Inc., “TurboBIST-Memory and Built-in Self-test Generator,” 2011.
[20]K. L. Cheng, C. M. Hsueh, J. R. Huang, J. C. Yeh, C. T. Huang, and C. W. Wu, “Automatic generation of memory built-in self-test cores for system-on-chip,” in Proc. IEEE Asian Test Symp. (ATS), pp. 91–96, Nov. 2001.
[21]J. M. Rabaey, A.Chandrakasan, and B. Nikolic “Digital Integrated Circuits,” Pearson Education Taiwan Ltd.
[22]Micron, “1Gb: x4, x8, x16 DDR3 SDRAM,” http://www.micron.com/resource-details/31780d73-ea30-4400-af00-86e22c6c22ea
[23]Micron, “2Gb: x4, x8, x16 DDR3 SDRAM,” http://www.micron.com/resource-details/e39e9941-4d9e-426a-9aca-d65a25a01794
[24]Micron, “4Gb: x4, x8, x16 DDR3 SDRAM,” http://www.micron.com/resource-details/2adceeb1-307f-4b37-99c9-7302caa8bc5c
[25]I. Koren and C. M. Krishna, “Fault Tolerant Systems,” Morgan-Kaufman.