本論文主要探討光通訊矽鍺基接收端積體電路的設計與實現，其中包含光檢測晶片、突發式增益自動控制轉阻放大器與限幅放大器。
第一部份利用矽基CMOS製程設計光檢測晶片，使用製程為台積電(TSMC) 0.18μm CMOS 1P6M，利用CMOS製程中NMOS做為檢光二極體，以結構內的p-n接面設計提昇檢光效果。
第二部份利用矽鍺基BiCMOS製程實現矽基光檢測晶片，使用製程為台積電(TSMC) 0.35μm SiGe BiCMOS，進而探討光電晶體的電流增益特性與佈局。量測結果顯示該光檢測晶片可以操作在1V的供應電壓，在0.45mm×0.45mm有效照射面積下，響應度650nm±14nm時為1.85A/W，850nm±14nm時為1.207A/W。
第三部份為轉阻放大器(TIA)及限幅放大器(LA)的實現，使用製程為(TSMC) 0.35μm SiGe BiCMOS，電路中採用RGC架構作為主要輸入級，有效隔絕了輸入的寄生電容，藉以提高頻寬表現，並加入限幅放大器(LA)提高輸出電壓振幅，並將輸出電壓限制在數位訊號位準上。當供應電壓3.3V與輸入電容0.25pF時，在頻寬為2.60GHz下，增益為84.80 dBΩ，資料傳輸(Bit Rate)可達3.0Gbps，總功率消耗102.2mW。
第四部份利用RGC架構設計，加上了增益可調轉阻放大器(VGA)，以及設計突發式增益自動控制電路(AGC)。使用製程為台積電(TSMC) 0.18μm CMOS 1P6M。以供應電壓1.8V與輸入電容0.25pF模擬時，動態增益範圍63.3~81.2 dBΩ，對應動態頻寬為4.92~5.41GHz，總功率消耗95.82mW。

This paper discusses the design and realization of SiGe-based optical receiving integrated circuit, including photodetector, burst-mode automatic-gain controlled (AGC) transimpedance amplifier (TIA) and limiting amplifier (LA).

First, we use the TSMC 0.18μm CMOS 1P6M process to realize silicon photodetection circuit design. We use NMOS in the CMOS process to design photodiode, utilizing P-N junctions in the structure to achieve photodiode characteristics.

Secondly, we use the TSMC 0.35μm SiGe BiCMOS process to realize the silicon photodetection circuit. Discussion is made on the current gain property and layout of phototransistor. Measurement results show that the photodetector can be operated at power supply lower than 1V, while responsibilityies are 1.85A/W at 650nm±14nm and 1.207A/W at 850nm±14nm for the detector with the area 0.45mm×0.45mm.

Thirdly, the TIA and LA realization using the TSMC 0.35μm SiGe BiCMOS process is made. The RGC type is used as input stage in the circuits. It effectively isolates input parasitic capacitance, and therefore increases bandwidth performance. By adding LA, the output swing is raised and restricts output voltage on the logic level. At 3.3V and 0.25pF input capacitance, the bandwidth is 2.60GHz for a gain of 84.80 dBΩ, the bit rate 3.0Gbps, and the total power consumption is 102.2mW.

Finally, are show a design of a burst-mode silicon receiving circuit using RGC-type TIA with variable gain amplifier (VGA). We use the TSMC 0.18μm CMOS 1P6M process. At 1.8V and 0.25pF input capacitance in our simulation, the dynamic gain range is 63.3~81.2 dBΩ, the corresponding dynamic bandwidth range 4.92~5.41GHz, the total power consumption is 95.82mW.

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