本論文使用TSMC 90奈米CMOS製程技術設計並實現應用於先進無線通訊之可程式增益放大器。發射機端可程式增益放大器在1.2 pF電容負載下的-3 dB頻寬為2.2 GHz，由5-bit 數位電路切換電壓增益範圍為-18 dB~ 2 dB，單位切換增益為1 dB，S21為-15.79 ~ 3.01 dB。在1.2 V電源供應下，電路功耗為22.7 mW。晶片面積為0.999 mm2。 接收機端可程式增益放大器在1 pF電容負載下的-3 dB頻寬為2 GHz，由5-bit 數位電路切換電壓增益範圍為13.5 dB ~ 60 dB，單位切換增益為1.5 dB。在1.2 V電源供應下，電路功耗為39 mW。晶片面積為0.8 mm2。

Two types of programmable-gain baseband amplifier (PGA) are designed and implemented using TSMC 90-nm CMOS technology for advanced wireless communication. Transmitter PGA measurement achieves the voltage gain range of -18~2 dB in steps of 1 dB, S21 of -15.79~3.01 dB. -3 dB bandwidth of 2.2 GHz with 1.2 pF capacitive load, controlled by 5-bits decoder. With a 1.2 V supply, the circuit consumes 22.7 mW. The chip area is 0.999 mm2. Receiver PGA simulation achieves the voltage gain range of 13.5~60 dB in steps of 1 dB, -3 dB bandwidth of 2 GHz with 1 pF capacitive load, controlled by 5-bits decoder. With a 1.2 V supply, the circuit consumes 39 mW. The chip area is 0.8 mm2.

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