由於快閃記憶體技術已縮小到 1x nm，並且可以在一個單元中存儲更多位，因此快閃記憶體的存儲密度得到了顯著提高。然而，這些技術趨勢也嚴重損害了快閃記憶體的編程速度和耐久性。內部數據保留時間是快閃記憶體單元可以正確保存數據的持續時間。通過放鬆內部數據保留時間，可以提高頁面編程速度和塊耐用性。然而，根據工業標準，快閃的保留時間通常需要持續數年。因此需要一個刷新方案來處理保留時間的減少。本文的第一部分提出了具有鬆弛管理（RTR）方案的多級保留時間隊列，以滿足可靠存儲系統的保留時間要求。根據我們的實驗結果，所提出的 RTR 方案不僅可以顯著提高快閃存儲系統的耐久性和性能，還可以顯著提高其能耗。除了工藝縮放和每單元多位技術，學術界和工業界都開始發展3D堆疊技術，以進一步提高快閃記憶體的存儲密度。然而，隨著堆疊層數和存儲密度的增加，3D快閃記憶體也面臨更高的原始誤碼率 (RBER) 和更短的使用壽命。觀察到可靠的單元狀態具有較少的程序干擾和數據保留錯誤，本論文的第二部分提出了一種具有非對稱編碼（DEA-AC）方案的差分演化演算法，以增加將數據存儲在更可靠的單元狀態中的概率，從而減少RBER。實驗結果顯示，與基線、ACA、ACS-SPEA、UAC-nLC、WBMP、和 SCB 方案相比較，建議方案可分別平均減少48.88%, 65.45%, 52.61%, 61.99%, 80.19%, and 33.18%的RBER。

As flash memory technology has been scaled down to 1x nm and more
bits can be stored in a cell, the storage density of flash memory has been significantly improved. However, these technical trends also severely hurt the
programming speed and endurance of flash memory. The internal data retention
time is the duration for which a flash cell can correctly hold data. By
relaxing internal data retention time, both the page programming speed and
the block endurance could be improved. However, the retention time of flash
memory typically requires to last for several years according to the industrial
standard. Thus a refreshment scheme is required to deal with the decreasing
of retention time. The first part of this dissertation proposes multi-level
retention-time queues with a relaxation management (RTR) scheme to meet
the retention-time requirement for a reliable storage system. Based on our
experimental results, not only endurance and performance but also energy
consumption of the flash-memory storage system could be significantly improved
by the proposed RTR scheme. In addition to the process scaling and
multi-bits per cell technologies, both academia and industry have begun to
develop 3D stacking technology to further increase the storage density of
flash memory. However, as the number of stacked layers and storage density
increase, 3D flash memory also suffers from a higher raw bit error rate
(RBER) and a shorter lifetime. Observing that reliable cell states have less
program disturbance and data retention errors, the second part of this dissertation proposes a differential evolution algorithm with asymmetric coding
(DEA-AC) scheme to increase the probability of storing data in more reliable
cell states, thereby reducing the RBER. The experimental results showed
that the proposed DEA-AC scheme could averagely reduce RBER by 48.88%,
65.45%, 52.61%, 61.99%, 80.19%, and 33.18% compared with baseline, ACA,
ACS-SPEA, UAC-nLC, WBMP, and SCB schemes.

[1] Y. Luo, Y. Cai, S. Ghose, J. Choi, and O. Mutlu, “WARM: Improving NAND Flash Memory Lifetime with Write-hotness Aware Retention Management,” in Mass Storage Systems and Technologies (MSST), May 2015, pp. 1–14.
[2] Y. Cai, E. F. Haratsch, O. Mutlu, and K. Mai, “Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis,” in Design Automation and Test in Europe Conference (DATE), March 2012, pp. 521–526.
[3] Y. Pan, G. Dong, Q. Wu, and T. Zhang, “Quasi-Nonvolatile SSD: Trading Flash Memory Nonvolatility to Improve Storage System Performance for Enterprise Applications,” in IEEE International Symposium on High-Performance Comp Architecture (HPCA), February 2012, pp.1–10.
[4] S. Bennett and J. Sullivan, “The Characterisation of TLC NAND Flash Memory, Leading to a Definable Endurance/Retention Trade-Off,” International Journal of Computer, Electrical, Automation, Control and Information Engineering, vol. 10, p. 8, 2016.
[5] J.-H. Kim, S.-H. Kim, and J.-S. Kim, “Subpage Programming for Extending the Lifetime of NAND Flash Memory,” in Design, Automation Test in Europe Conference Exhibition (DATE), March 2015, pp. 555–560.
[6] H. Nazarian and C. Sylvain Dubois, “The Drive for SSDs: What’s Holding Back NAND Flash,” https://www.edn.com/Home/PrintView?contentItemId=4424905, p. 1, November 2013.
[7] N. R, K. J, and K. R, “NAND Flash Memory Organization and Operations,” in Journal of Information Technology and Software Engineering, January 2015, pp. 5–139.
[8] K. Mizoguchi, T. Takahashi, S. Aritome, and K. Takeuchi, “Data-Retention Characteristics Comparison of 2D and 3D TLC NAND Flash Memories,” in 2017 IEEE International Memory Workshop (IMW), May 2017, pp. 14–17.
[9] L. Shi, K.Wu, M. Zhao, C. J. Xue, D. Liu, and E. H. M. Sha, “Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 1, January 2016.
[10] Y. Cai, Y. Luo, E. F. Haratsch, K. Mai, and O. Mutlu, “Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery,” in 2015 IEEE 21st International Symposium on High-Performance Computer Architecture (HPCA), February 2015, pp. 551–563.
[11] Y. Di, L. Shi, K. Wu, and C. J. Xue, “Exploiting Process Variation for Retention Induced Refresh Minimization on Flash Memory,” in Design, Automation Test in Europe Conference Exhibition (DATE), March 2016, pp. 391–396.
[12] J.-W. Hsieh, C.-W. Chen, and H.-Y. Lin, “Adaptive ECC Scheme for Hybrid SSD’s,” IEEE Transactions on Computers, vol. 64, pp. 3348–3361, December 2015.
[13] T. Tokutomi, S. Tanakamaru, T. O. Iwasaki, and K. Takeuchi, “Advanced Error Prediction LDPC for High-speed Reliable TLC Nand-Based SSDs,” in 2014 IEEE 6th International Memory Workshop (IMW), May 2014, pp. 1–4.
[14] M. Doi, S. Tanakamaru, and K. Takeuchi, “A Scaling Scenario of Asymmetric Coding to Reduce Both Data Retention and Program Disturbance of NAND Flash Memories,” in Solid-State Electronics (SSE), February 2014, pp. 63–69.
[15] K. Mizushina, T. Nakamura, Y. Deguchi, and K. Takeuchi, “Layer-by-Layer Adaptively Optimized ECC of NAND Flash-Based SSD Storing Convolutional Neural Network Weight for Scene Recognition,” in 2018 IEEE International Symposium on Circuits and Systems (ISCAS), May 2018, pp. 1–5.
[16] S. Yamazaki, S. Tanakamaru, S. Suzuki, T. O. Iwasaki, S. Hachiya, and K. Takeuchi, “Reliability Enhancement of 1Xnm TLC for Cold Flash and Millennium Memories,” in 2015 Symposium on VLSI Circuits (VLSI Circuits), June 2015, pp. T112–T113.
[17] E. H.-M. Sha, C. Gao, L. Shi, K. Wu, M. Zhao, and C. J. Xue, “Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems,” IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 36, no. 8, pp. 1–13, AUGUST 2017.
[18] K.-D. Suh, B.-H. Suh, Y.-H. Lim, J.-K. Kim, Y.-J. Choi, Y.-N. Koh, S.-S. Lee, and J.-S. Yum, “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 1149–1156, November 1995.
[19] Y. Cai, G. Yalcin, O. Mutlu, E. F. Haratsch, A. Cristal, O. S. Unsal, and K. Mai, “Flash Correct-and-Refresh: Retention-Aware Error Management for Increased Flash Memory Lifetime,” in Computer Design (ICCD), September 2012, pp. 94–101.
[20] X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie, “Hybrid Cache Architecture with Disparate Memory Technologies,” in Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09), 2009, pp. 34–45.
[21] B. Govoreanu, G. S. Kar, Y. Y. Chen, V. Paraschiv, S. Kubicek, A. Fantini,
I. P. Radu, L. Goux, S. Clima, R. Degraeve, N. Jossart, O. Richard, T. Vandeweyer, K. Seo, P. Hendrickx, G. Pourtois, H. Bender, L. Altimime, D. J. Wouters, J. A. Kittl, and M. Jurczak, “10x10nm2 Hf/HfOx Crossbar Resistive RAM with Excellent Performance, Reliability and Low-Energy Operation,” in 2011 International Electron Devices Meeting, December 2011, pp. 31.6.1–31.6.4.
[22] P. Chi, S. Li, Y. Cheng, Y. Lu, S. H. Kang, and Y. Xie, “Architecture Design
with STT-RAM: Opportunities and Challenges,” in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), January 2016, pp. 109–114.
[23] W. Xu, H. Sun, X. Wang, Y. Chen, and T. Zhang, “Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM),” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 3, pp. 483–493, March 2011.
[24] Y. H. Song, S. Jung, S.-W. Lee, and J.-S. Kim, “Cosmos OpenSSD: A PCIe-based Open Source SSD Platform,” in Flash Memory Summit, August 2014, p. 12.
[25] A. Gupta, Y. Kim, and B. Urgaonkar, “DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings,” in Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems. ACM, March 2009, pp. 229–240.
[26] A. Silberschatz, P. B. Galvin, and G. Gagne, Operating System Concepts 8th Edition. Pergamon Press and Oxford, 2009.
[27] A. Fukami, S. Ghose, Y. Luo, Y. Cai, and O. Mutlu, “Improving the Reliability of Chip-off Forensic Analysis of NAND Flash Memory Devices,” Digital Investigation, vol. 20, pp. S1 – S11, January 2017.
[28] T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction
to Algorithms - Third Edition. The MIT Press, 2009.
[29] R.-S. Liu, C.-L. Yang, and W. Wu, “Optimizing NAND Flash-Based SSDs via Retention Relaxation,” in FAST’12: Proceedings of the 10th USENIX conference on File and Storage Technologies, February 2012, p. 11.
[30] S. Senni, L. Torres, G. Sassatelli, A. Gamatie, and B. Mussard, “Emerging
Non-volatile Memory Technologies Exploration Flow for Processor Architecture,” in 2015 IEEE Computer Society Annual Symposium on VLSI, July 2015, pp. 460–460.
[31] H. Lee, J. G. Alzate, R. Dorrance, X. Q. Cai, D. Markovic, P. Khalili Amiri, and K. L. Wang, “Design of a Fast and Low-Power Sense Amplifier and Writing Circuit for High-Speed MRAM,” IEEE Transactions on Magnetics, vol. 51, no. 5, pp. 1–7, May 2015.
[32] L.-P. Chang, “A Hybrid Approach to NAND-Flash-Based Solid-State Disks,” IEEE Transactions on Computers, vol. 59, pp. 1337–1349, January 2010.
[33] L.-P. Chang and C.-D. Du, “Design and Implementation of an Efficient Wear-Leveling Algorithm for Solid-State-Disk Microcontrollers,” ACM Transactions on Design Automation of Electronic Systems, vol. 15, pp.6:1–6:36, December 2009.
[34] UMassTraceRepository, “Oltp Applications of two Financial Institutions,”
http://traces.cs.umass.edu/index.php/Storage/Storage/, p. 1, 2007.
[35] Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu, “Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives,” Proceedings of the IEEE, vol. 105, no. 9, pp. 1666–1704, September 2017.
[36] S. Tanakamaru, Y. Kitamura, S. Yamazaki, T. Tokutomi, and K. Takeuchi, “Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs),” IEEE Trans. on Circuits and Systems, vol. 62-I, no. 3, pp. 771–780, March 2015.
[37] L. Feng, “Data Storage Device and Data Scrambling and Descrambling Method,” Patent No. US9582670B2 VIA TECHNOLOGIES, INC.,, pp.1–10, February 2017.
[38] A. Qing, Fundamentals of Differential Evolution. IEEE, 2009, pp. 41–60.
[39] S. Tanakamaru, C. Hung, and K. Takeuchi, “Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming,” IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp. 85–96, January 2012.
[40] S. Tanakamaru, Y. Kitamura, S. Yamazaki, T. Tokutomi, and K. Takeuchi, “Application-Aware Solid-state Drives (SSDs) with Adaptive Coding,” in Symposium on VLSI Circuits, June 2014, pp. 1–2.
[41] Y. Deguchi and K. Takeuchi, “Word-Line Batch Vth Modulation of TLC NAND Flash Memories for Both Write-Hot and Cold Data,” in 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), November 2017, pp. 161–164.
[42] K. Mizoguchi, K. Maeda, and K. Takeuchi, “Automatic Data Repair Overwrite Pulse for 3D-TLC NAND Flash Memories with 38x Data-Retention Lifetime Extension,” in IEEE International Reliability Physics Symposium, IRPS 2019, Monterey, CA, USA, March 31 - April 4, 2019, October 2019, pp. 1–5.
[43] Y. Luo, S. Ghose, Y. Cai, E. Haratsch, and O. Mutlu, “HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness,” in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), February 2018.
[44] S. Yang, J. Kurose, and B. N. Levine, “Disambiguation of Residential Wired and Wireless Access in A Forensic Setting,” in Proc. IEEE INFOCOM Mini-Conference, April 2013, pp. 1–5.
[45] N. Banerjee, M. D. Corner, D. F. Towsley, and B. N. Levine, “Relays, Base Stations, and Meshes: Enhancing Mobile Networks with Infrastructure,” in ACM MobiCom, September 2008, pp. 81–91.
[46] L. Schiff, O. Ziv, M. Jaeger, and S. Schmid, “NetSlicer: Automated and Traffic-Pattern Based Application Clustering in Datacenters,” in Proc. ACM SIGCOMM 2018 Workshop on Big Data Analytics and Machine Learning for Data Communication Networks (Big-DAMA), August 2018, pp. 21–26.
[47] T. Benson, A. Akella, and D. A. Maltz, “Network Traffic Characteristics of Data Centers in The Wild,” in ACM Internet Measurement Conference, November 2010, pp. 267–280.