研究生: |
曾佑民 Yu-min Tseng |
---|---|
論文名稱: |
無量測器直流無刷馬達控制之FPGA設計與製作 FPGA Design and Implementation for the Sensorless Control of a DC Brushless Motor |
指導教授: |
劉昌煥
Chang-Huan Liu |
口試委員: |
施慶隆
Ching-Long Shih 胡龍融 none |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2005 |
畢業學年度: | 93 |
語文別: | 中文 |
論文頁數: | 100 |
中文關鍵詞: | 直流無刷馬達 、有量測器控制 、無量測器控制 、現場可程式邏輯閘陣列,數位訊號處理器 |
外文關鍵詞: | sensor-ed control |
相關次數: | 點閱:530 下載:14 |
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本研究以VHDL硬體描述語言分別設計有量測器和無量測器的直流無刷馬達控制法則,再使用Altera Quartus II發展軟體於FPGA硬體上,實現所設計的數位電路。控制法則設計方法是將馬達啟動程序和各個功能分成多個模組,設計完成後再加以整合,依據各功能所需的精確度以1至21位元無號定點(fixed-point)數表示。
在實驗系統發展上,除了以FPGA進行馬達控制的數位電路設計外,並搭配DSP系統,形成一DSP-FPGA混合系統。系統設計步驟是先根據DSP系統實現各個功能,FPGA只負責PWM責任週期產生器,之後則將大部分功能都移植到FPGA上,DSP只負責控制器與啟動開關。所發展的系統可以在有量測器和無量測器模式下,配合零交越點偵測電路和功率級板,使馬達順利運轉。
本論文所得之實驗結果,在轉速130 r/min以上,有量測器控制模式在4000 r/min以下,無量測器控制模式在2750 r/min以下,都可以達到快速且穩定的速度響應。根據本論文之結果,未來可設計更先進的控制器於FPGA上,以朝向系統晶片化(SOC)邁進,降低成本和體積。
This thesis applies VHDL (Very High Speed Integrated Circuits Description Language) to design control algorithms for sensor-ed and sensorless dc brushless motors, which are further implemented on an FPGA using Altera Quartus II so as to realize the digital circuits. The design approach for the control algorithms is to divide the motor start-up and various other functions into modules, which are designed individually and then integrated together. Each function is represented in one-bit to 21-bit fixed-point formats, depending on the accuracy requirement.
On the development of the experimental setup, the FPGA is used to realize the digital circuits of motor control. The FPGA is assisted by a DSP to form a DSP-FPGA hybrid system. The system design procedure is first to realize various functions using the DSP and the FPGA is only responsible for PWM duty cycle generation. These functions are then re-implemented on the FPGA with the DSP responsible for startup and controller only. The developed system, assisted by the zero-crossing detection circuit and a power board, can successfully operate the motor under sensor-ed and sensorless control modes.
The experimental results show that, for speed control above 150 r/min, stable speed responses can be achieved for sensor-ed speed control below 4000 r/min and for sensorless speed control below 2750 r/min. For future development, more advanced controllers can be implemented on the FPGA and system-on-chip (SOC) can be considered so as to reduce cost and size.
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