近幾年來，隨著科技的進步，可攜式影音產品的功能越來越多，漸漸地成為人們生活中不可或缺的一部分，但由於電池供電的成長趨勢，不及於產品的耗能速度，因此低功率的設計產品概念逐漸受到重視。而JPEG是影音裝置常見且受歡迎的影像壓縮標準之一，所有JPEG圖片皆須經過霍夫曼編碼(Huffman coding)與解碼程序以達到壓縮的目的，所以低功率交流(AC)霍夫曼解碼器設計有其必要性與重要性。
在JPEG交流霍夫曼解碼器的架構中，霍夫曼查表區塊(LUT)所佔據面積最大、動作頻率最高，所以最耗電的部分就是LUT，因此本論文引用表格分割法的觀念，利用二分法的架構(bipartition architecture)於LUT中，在經過改善後，實現一個低耗能與兼顧高速率的JPEG AC 霍夫曼解碼器。
最後，經由TSMC 0.13-um, 1.3V 元件庫(technology library)進行硬體合成，與Synopsys PrimePower模擬結果，顯示本論文所提出的架構較傳統式架構，最多可以減少25%的功率消耗，而解碼速度可以高達125MHz，此外面積幾乎沒有太大改變。因此本論文所提出的架構，非常適合使用在需要低功率且高速率的JPEG 交流霍夫曼解碼器應用中，尤其是可攜式產品應用。

In recent years, the increased demand for portable multimedia devices has made power a very important factor. JPEG is one of the most popular and successful image compression standards for storage and communication application. In this paper, a simple yet successful design for a JPEG alternating current (AC) Huffman decoder with low power and high performance is presented.

In conventional JPEG AC Huffman decoder circuits, the most area and power intensive portion of the system is in the Huffman LUT block. Based on the parallel Huffman decoder structure, we introduced a bipartition architecture into the lookup table (LUT) to attain low power consumption without sacrificing decoding performance.

By using Synopsys PrimePower with TSMC 0.13-um, 1.3-V technology library at 125MHz decoding speed to estimate the power consumption, the gate level power simulation results show a maximum of 25% power reduction as compared to a conventional JPEG parallel Huffman decoder. Therefore, our approach can be used in low power and high throughput JPEG decoding applications, especially in battery-based system design.

[1] 戴顯權, 資料壓縮, 紳藍出版社, 2002.
[2] 陳同孝, 張真誠, 黃國峰, 數位影像處理技術, 松崗電腦圖書, 2001
[3]V. Bhaskaran and K. Konstantinides, “Image and video compression standards algorithm and architectures,” Kluwer Academic, 1999. IEICE TRANS. FUNDAMENTALS, VOL.E86–A, NO.5 MAY 2003
[4]D.A. Huffman, “A method for the construction of minimum- redundancy codes,” Proc. Institute of Radio Engineers(IRE), vol.40, pp.1098–1101, Sept. 1952.
[5]S.M. LEI and M.T. SUN, “An entropy coding system for digital HDTV applications,” IEEE Trans. Circuits and Systems for Video Technology, vol.1, pp.147–155, Mar. 1991.
[6]S.B. Choi and M.H. Lee, “High speed pattern matching for a fast huffman decoder,” IEEE Trans. Consum. Electron, vol.41, pp.97 – 103, Feb. 1995.
[7]J.H. Jiang, C.C. Chang, and T.S. Chen, “An efficient huffman decoding method based on pattern partition and lookup table,” Fifth Asia-Pacific Conf. on Communications and Fourth Optoelectronics and Communications, pp.904–907, Oct. 1999.
[8]Y.W. Chang, T.K. Truong, and Y. Chang, “Direct mapping architecture for jpeg huffman decoder,” IEE Proc. Communications, vol.153, pp.333–340, June 2006.
[9] Shih-Fu Chang and David G, “Designing high-throughput VLC decoder part I-concurrent VLSI architectures,” IEEE Trans. Circuits and Systems for Video Technology, vol. 2, no. 2, pp.187-196, June 1992.
[10] Aspar Z, Yusof Z M, Suleiman I, “Parallel Huffman decoder with an optimize look up table option on FPGA,” TENCON 2000 Proceedings[C] , 2000.1:73-76.
[11] Bai-Jue, S., L. Yew-San, and L. Chen-Yi, “A new approach of group-based VLC codec system with full table programmability,” Circuits and Systems for Video Technology, IEEE Transactions on, p. 210-221, 2001.
[12] Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha, “Multiple-symbol parallel decoding for variable length codes,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 7, pp. 676-685, July 2004.
[13] R. Hashemian. “Design and hardware implementation of a memory efficient Huffman decoding,” IEEE Trans. Consumer Electronics, vol. 40, no. 3, pp. 345-352, Aug. 1994.
[14]Pi-Chung Wang, Yuan-Rung Yang, Chun-Liang Lee, and Hung-Yi Chang, "A Memory-efficient Huffman Decoding Algorithm," IEEE AINA'2005, Tamkang University, Taiwan, March 2005, pp. 475-479.
[15] Yuh-Jue Chuang, Ja-Ling Wu, “An SGH-Tree Based Efficient Huffman Decoding,” Proceeding of the 4th International Conference on Information, Communications & Signal Processing 4th IEEE Pacific-Rim Conference On Multimedia(ICICS-PCM), vol 3, pp. 1483-1487, 2003. (EI)
[16] Yuh-Jue Chuang and Ja-Ling Wu, “An SGH-Tree Based Memory Efficient and Constant Decoding Algorithm for Huffman Codes”, the 2004 International Symposium on Intelligent Multimedia, Video & Speech Processing (ISIMP 2004), HK, Oct. 2004.
[17] P.C. Wang, C.L. Lee, Y.R. Yang and H.Y Chang, "CAM-based Huffman Decoding Made Power Efficient," IEEE AINA'2005, Tamkang University, Taiwan, March 2005, pp. 909-914.
[18]Y. Ooi, A. Taniguchi, and S. Demura, “A 162 mbit/s variable length decoding circuit using an adaptive tree search technique,” Proc. IEEE Custom Integrated Circuits Conf., pp.107–110, May 1994.
[19] CHO, S.-H., Xanthopoulos, T., and Chandrakasan, A.P.: “Design of low power variable length decoder using fine grain non-uniform table partitioning,” IEEE Int. Symp. Circuits and Systems, pp. 2156-2159, 1997
[20]S.H. Cho, T. Xanthopoulos, and A.P. Chandrakasan, “A low power variable length decoder for mpeg-2 based on nonuniform fine-grain table partitioning,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol.7, pp.249–257, June 1999.
[21] C.H.Lin and C.W.Jen, 1998 "Low Power Parallel Huffman Decoding," Electronics Letter, Vol.34,No.3,pp.240-241
[22]S.W. Lee and I.C. Park, “A low-power variable length decoder for mpeg-2 based on successive decoding of short codewords,” IEEE Trans. Circuits and Systems, vol.50, pp.73–82, Feb. 2003.
[23] S.J. Ruan, K.L. Tsai, E. Naroska and F. Lai, "Bipartitioning and Encoding in Low Power Pipelined Circuits," ACM Trans. on Design Automation of Electronic Systems, Vol. 10, No.1, pp 24-32, Jan. 2005. (NSC 92-2218-E-011 -006 ) (SCI)
[24] S.J. Ruan, R.J. Shang, F. Lai, S.J. Chen., and X.J. Huang, “A bipartition-codec architecture to reduce power in pipelined circuits,” Proc. IEEE/ACM Int. Conf. Computer-Aided Design, pp.84–89, Nov. 1999.
[25] S.J. Ruan, R.J. Shang, F. Lai, S.J. Chen., and X.J. Huang, “A bipartition-codec architecture to reduce power in pipelined circuits,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.20, no.2, pp.343– 348, Feb. 2001.