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研究生: 陳俊致
Chun-Chih Chen
論文名稱: 低功率預先計算內容可定址記憶體之合成
Synthesis of Low Power PB-CAM
指導教授: 阮聖彰
Shanq-Jang Ruan
口試委員: 許孟超
Mon-Chau Shie
楊佳玲
Chia-Lin Yang
張延任
Yen-Jen Chang
陳宏明
Hung-Ming Chen
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2006
畢業學年度: 94
語文別: 英文
論文頁數: 34
中文關鍵詞: 預先計算可定址記憶體低功率區塊選擇演算法受測程式
外文關鍵詞: low power, PB-CAM, Gate-Block-Selection Algorithm, benchmark
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由於平行比對使得Content addressable memory (CAM)有快速的資料搜尋速度。因此Content addressable memory (CAM)被廣泛的應用在很多方面,例如:asynchronous transfer mode (ATM), communication networks, LAN bridges/switches , databases, lookup table , and tag directories in fully associative cache systems。然而平行比對總是消耗較多功率的。於是本篇論文提出了一個Gate-Block-Section Algorithm。此方法以Precomputation-Based Content Addressable Memory(PB-CAM)架構為基礎,透過gate block的選擇來減少平行比對次數。依據程式模擬的結果,本篇論文的方法可以減少19.0%~26.6%的平行比對次數。在實驗過程中,使用TSMC 0.18μm,1.8V。為求精準,本論文使用Synopsys Nanosim量測功率。由實驗結果顯示,本篇論文的方法可以節省3.1%~13.3%的功率。這篇文章主要的目的是提供理論和實際的證據驗證Gate-Block-Selection Algorithm可以進一步針對不同的benchmark節省功率。因此我們的Gate-Block-Selection Algorithm非常適用於嵌入式系統。


Content addressable memory (CAM) is a major device in asynchronous transfer mode
(ATM), communication networks, LAN bridges/switches , databases, lookup table ,
and tag directories in fully associative cache systems, due to its high-speed parallel
data searching operation. Hence, the operation of CAM requires an enormous number
of comparison operations. Obviously, these comparison operations consumes a large
amount of power.
In this paper, we propose a Gate-Block-Selection algorithm to construct a low
power PB-CAM to reduce the comparison operation number. By our theoretical
analysis, we can reduce 19.0 % at least, 26.6 % at most. the total number of the
comparison operation of our Gate-Block-Selection algorithm is much less than that
of the Block-XOR approach. Moreover, we implemented both the Block-XOR PBCAM
and our Gate-Block-Selection PB-CAM in the TSMC 0.18-μm digital CMOS
process technology and measure the power consumption by Nanosim. Compared to
Block-XOR approach, the experimental result shows that our Gate-Block-Selection
PB-CAM comsumes 3.1% at least and 13.3% at most less power than Block-XOR
does.
The major contribution of our paper is that we provided theoretical and practical
proof to verify that our gate-block-selection approach can further reduce the power
consumption to fit different benchmark. Therefore, our Gate-Block-Selection PBCAM
is very suitable for embedded systems.

Table of Contents iv Abstract v 1 Introduciton 1 2 Previous Work and Observation 7 3 Problem Formulation 10 3.1 Gate-Block-Selection Algorithm . . . . . . . . . . . . . . . . . . . . . 11 3.2 Valid Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 CAMCIRCUITDESIGN 17 5 Experimental Results 23 5.1 Experimental Environment . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 Theoretical Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 Power ConsumptionMeasured by Nanosim . . . . . . . . . . . . . . . 25 6 Conclusions 27 Bibliography 29

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