邏輯記憶體堆疊之三維積體電路之有效測試與修復技術

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研究生：	彭聖文 Sheng-wen Peng
論文名稱：	邏輯記憶體堆疊之三維積體電路之有效測試與修復技術 Efficient Test and Repair Architectures for Logic-Memory Stacked 3D ICs
指導教授：	呂學坤 Shyue-Kung Lu
口試委員:	王乃堅 Nai-Jian Wang 郭斯彥 Sy-Yen Kuo 洪進華 Jin-Hua Hong 李進福 Jin-Fu Li
學位類別：	碩士 Master
系所名稱：	電資學院 - 電機工程系 Department of Electrical Engineering
論文出版年：	2013
畢業學年度：	101
語文別：	英文
論文頁數：	76
中文關鍵詞：	三維記憶體、記憶體堆疊、修復技術、測試技術
外文關鍵詞：	3D-IC, memory stack, test, repair
相關次數：	點閱：352 下載：12
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隨著積體電路 (Integrated Circuit, IC) 設計技術的進步，電路越來越複雜，積體電路設計工程師所需要處理的問題越來越多，包含繞線與功率消耗的問題。而在二維積體電路 (2-Dimensional IC, 2D IC) 的設計當中，設計已經逐漸遇到瓶頸。三維積體電路 (3-Dimensional IC, 3D IC) 的出現為此困境帶來改善的契機。與傳統二維積體電路比較，三維積體電路的設計在繞線長度、電路表現與功率的耗損上，都有著二維積體電路比不上的優勢。然而，新的技術的發展同時也帶來了許多問題，三維積體電路技術的發展讓電路的複雜度更加提升，隨技術而產生的許多的測試和良率的問題還需要被解決。.
在這篇論文當中，我們設計了一個三維積體電路的測試與修復架構，主要針對記憶體堆疊 (Memory Stack) 與邏輯裸晶的堆疊型式，這個測試架構是以IEEE 1149.1邊界掃描與IEEE 1500 為基礎設計的，我們可以簡單地把整個三維架構中區分為僕裸晶 (Slave Die) 與主裸晶 (Master Die)，僕裸晶包含了記憶體、內建自我測試 (Built-In Self-Test, BIST) 模組與內建備用資源分析 (Built-In Redundancy Analysis, BIRA) 模組與IEEE 1149.1介面，而主裸晶中則包含了一個處理器、重組電路 (Remapping Circuit)、主裸晶控制器與 IEEE 1500 介面。在這樣的設計當中，我們能夠透過 IEEE 1500 介面對主裸晶中的處理器與其他邏輯電路進行測試，也能夠對重組電路進行記憶體的重組設定。為了減少測試墊 (Test Pad) 與直通矽晶穿孔的使用量，在僕裸晶中我們利用 IEEE 1149.1 介面命令記憶體中的內建自我測試與分析電路動作。我們的設計同時支援單獨晶片測試所需要的Known good die (KGD) 測試與晶片堆疊所需要的Known good stack (KGS) 測試與最終測試 (Final test)，且在僕裸晶的測試中，在這樣的設計中只需要四個測試腳位即可完成所有的測試動作。
這篇論文主要的貢獻在於我們利用一個簡單三維積體電路範例並且規劃其測試架構，希望能夠藉由這樣的範例中找出三維積體電路的測試準則。這些測試當中包含了記憶體的內建自我測試、備用記憶體分析與備用記憶體的配置方式。根據實驗結果顯示，在僕裸晶中的SRAM大小為8K × 32 位元的情況下，我們所額外加入的測試電路只有佔全部晶片的2.6%，而以 ARM926EJ 處理器為核心的主裸晶中，測試電路與備用記憶體的硬體成本也只有2.5%。而在我們的架構下所使用的晶圓堆疊演算法可以讓整體良率有著顯著的提升。

With the growing complexity of modern IC designs, IC designers need to handle a lot of problems such as power consumption, timing constraints, and routing complexity. The traditional 2D IC designs have been facing some design bottlenecks. Fortunately, with the emerging of 3D integrated circuits (3D ICs), most of these bottlenecks can be solved. As compared with the conventional planar designs, 3D-IC designs have a lot of advantages such as shorter wire lengths, higher performance, and lower power consumption. However, we need overcome several challenges of testing and yield since the 3D-ICs are more complex than the conventional 2D-ICs. The circuit is becoming enormous but the probe points are limited. Moreover, the manufacturing process is much different as compared to the 2D-ICs. There are still more problems we need to solve.
In this thesis, we propose a 3D-IC design-for-test (DfT) architecture based on IEEE 1149.1 and 1500 standards. The 3D-IC is separated into two parts. One is the CPU die or named the "master die." According to the application, the IEEE 1500 standard is implemented in this design. With the IEEE 1500 test interface, this architecture supports internal test, external test, and the memory reconfiguration mechanism. Another part is the memory dies or named the slave dies. The slave dies contains the main memory, the Built-In Self-Test (BIST) circuit, and the Built-In Redundant Analysis (BIRA) Circuit. In order to minimize the test pads and TSV usage, each slave die has a test interface based on the IEEE 1149.1 JTAG architecture. This interface supports KGD, KGS and final test. It only needs 4 test pads to conduct all the required test processes.
This thesis also presents a sample design which performs the KGD, KGS and final test. According to experimental results, the hardware overhead of the slave dies with 8K × 32-bit SRAM is only 2.6%. The hardware overhead of the master die (ARM926EJ CPU) with 8K-bit spare memory added is 2.5%. Moreover, the stacking yield can be improved significantly.

誌謝	I
摘要	II
Abstract	IV
Contents	VI
List of Figures	IX
List of Tables	XI
Chapter 1	Introduction	1
1	Motivation and Background	1
2	Organization	2
Chapter 2	Backgrounds	3
1	Review of Memory Technologies	3
2	Review of Fault Models and Test Algorithms	5
3	Review of Built-In Self-Repair Techniques	8
4	3D Integration Technology Using TSVs	10
4.1	Introduction	10
4.2	Processes	11
4.3	Circuit Stacking Techniques	13
4.4	Test Issues	14
5	IEEE 1149.1 Boundary Scan	15
5.1	Overview	15
5.2	Architecture	16
5.3	TAP Controller	17
6	IEEE 1500 Standard	18
6.1	Scalable Hardware Architecture	20
6.2	Test Instructions	21
7	DfT Architectures of ARM926EJ	23
8	Review of 3D-IC Test Interface Techniques	24
8.1	3D-IC DfT architecture based on IEEE 1500	25
8.2	3D-IC DfT architecture based on IEEE 1149.1	26
8.3	Operating Modes	28
Chapter 3	Test and Repair Techniques for 3D Logic-Memory Stacks	29
1	Slave Die Architecture	30
1.1	IEEE 1149.1 Interface	30
1.2	Dynamic Ordering	33
1.3	Instructions	35
1.4	BISR Flow for 3D Memory	37
1.5	Matching Algorithm	38
2	Master Die Architecture	43
2.1	Instructions	46
3	Test Flow and Boot Process	47
Chapter 4	Experimental Results	52
1	Matching Yield	52
2	Area Overhead	54
2.1	Area Overhead of the Slave Die	54
2.2	Area Overhead of the Master Die	55
3	VLSI Implementation	56
3.1	Slave Die Implementation	56
3.2	Master Die Implementation	57
Chapter 5	Conclusions	59
References	60

                                

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