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研究生: 鄭博文
Po-Wen Cheng
論文名稱: 使用FT601晶片重新設計OpenJTAG 轉換器
Re-Design the OpenJTAG Adaptor by Using FT601 Chip
指導教授: 林昌鴻
Chang-Hong Lin
口試委員: 王煥宗
Huan-Chun Wang
林其誼
Chi-Yi Lin
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2018
畢業學年度: 106
語文別: 中文
論文頁數: 98
中文關鍵詞: OpenOCDJTAGJlink
外文關鍵詞: OpenOCD, JTAG, Jlink
相關次數: 點閱:105下載:0
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在嵌入式系統開發過程中。有許多性能優越的調試,除錯工具,比如KEIL、IAR EWARM、Multi-IDE 等,這些軟件使用都很便利,功能強大,但是價格相對高昂(幾百美元甚至更多),此外尚須配購對應的 JTAG 轉換器(Joint Test Action Group)硬件如ARM 之RealView ICE (In Circuit Emulator),Segger Jlink 和 GreenHill 的 Multi-ICE對於學生族群,是一筆昂貴的支出。所幸一群軟體與硬件人員共襄盛舉開發出一套 OpenOCD (Open On Chip Debugger),MCU (Micro Controller Unit) base,FTDI base 之JTAG adapter。在眾多 adapter 中,OpenJTAG 是採FT245 USB (Universal SerialBus) 2.0 full speed 與CPLD (Complex Programmable Logic Device) 結合以減少控制JTAG pins 的傳送的資料量,但速度卻受限於 FT245,本文首先分析OpenJTAG傳輸速度的瓶頸,提供解決的方法,除了在通訊協定上增加新的指令集,並改採用新一代的USB 3.0 controller FT601 以解決硬體上的限制,使得資料傳輸速度比原始設計增加數倍。同時也闡述如何使用OpenOCD 的介面設計屬於自己的JTAG debugger,最後開發HDL (Hardware Description Language) Test Bench做為除錯和開發新指令的驗證工具。


In the process of embedded system development. There are many excellent debugging tools, such as KEIL, IAR EWARM, Multi-IDE, etc. These software are very convenient and powerful, but they are relatively expensive (several hundred dollars or more). In addition, the corresponding JTAG (Joint Test Action Group) Adaptor such as ARM's RealView ICE (In Circuit Emulator), Segger Jlink and GreenHill's Multi-ICE are required which is expensive for the students. Fortunately, a group of software and hardware personnel join the development of OpenOCD (Open On Chip Debugger) and create the MCU (Micro Controller Unit) base, FTDI base JTAG adapter. Among the many adapters, OpenJTAG is a combination of FT245 USB (Universal Serial Bus) 2.0 full speed and CPLD (Complex Programmable Logic Device) to reduce the amount of data transferred for JTAG pins control, but the speed is limited by FT245. This paper analyzes the bottleneck of OpenJTAG transfer speed, and provides a solution, in addition to adding a new instruction set to the protocol, and replace the USB bridge by using new generation of USB 3.0 bridge, FT601, to solve the hardware limitations, making the data transmission speed faster than the original design. The experimental results show the performance has dramatically increased. This paper also introduces how to design your own JTAG debugger by using OpenOCD's framework, and finally develops a HDL (Hardware Description Language) Test Bench as a verification tool for developing new instructions and debugging.

論文摘要 1 Abstract 2 目錄 5 圖索引 6 表索引 9 第一章 緒論 10 1.1 研究動機 10 1.2 研究方向與目的 11 1.3 研究貢獻 12 1.4 論文架構 13 第二章 相關背景知識 14 2.1 FT245 介紹 16 2.2 FT601 介紹 19 2.3 OpenJTAG 簡介 26 2.3.1 OpenJTAG 通訊協定 27 2.3.2 OpenJTAG 面臨的問題 35 2.4 OpenOCD介紹 41 2.4.1 OpenOCD 系統模組 41 2.4.2 OpenOCD 環境架設 43 2.4.3 OpenOCD 運作流程 46 第三章 FT601_JTAG ICE開發 50 3.1 開發平台 50 3.2 FT601_JTAG VHDL 實作 53 3.2.1 FT601_JTAG 通訊協定 53 3.2.2 FT601_JTAG FIFO 存取 57 3.2.3 FT601_JTAG 指令解碼 61 3.3 FT601_JTAG 介面程式 66 3.4 整合FT601 JTAG 至OpenOCD 76 3.5 FT601_JTAG Optimize_Level 定義 78 3.6 FT601 ModelSim Test Bench Design 80 3.6.1 開啟一個Modelsim的專案 80 3.6.2 FT601JTAG Test Bench 寫作 82 第四章 實驗測試與結果 85 4.1 FT601_JTAG 效能測試 86 4.2 Altera Virtual JTAG 90 第五章 結論與未來展望 93 參考資料 94

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全文公開日期 2026/08/06 (國家圖書館:臺灣博碩士論文系統)
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