新式四相位電壓控振盪器之設計｜國立臺灣科技大學博碩士論文系統

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研究生：	李岱松 Tai-Sung Lee
論文名稱：	新式四相位電壓控振盪器之設計 Design of Novel Quadrature Voltage-Controlled-Oscillators
指導教授：	徐敬文 Ching-Wen Hsue 張勝良 Sheng-Lyang Jang
口試委員:	黃進芳 Jhin-Fang Huang 陳凰美 Hwan-Mei Chen
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	114
中文關鍵詞：	四相位壓控振盪器、壓控振盪器、PLL
外文關鍵詞：	QVCO, VCO, PLL
相關次數：	點閱：360 下載：7
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上一筆

在通訊系統中，為了使頻寬能夠更有效利用，於是常將訊號分為I/Q兩通道。此外，為了減少雜訊干擾，系統大多採用差動型式，因此，在收發機的設計上就必須採用四相位的壓控振盪器才能夠進行訊號的解調。而對於壓控振盪器而言，低相位雜訊可以避免相鄰雜訊訊號經由混波轉換干擾，此外，低的功率消耗也是很重要的事情。在此本論文針對設計低相位雜訊與低功率消耗的四相位電壓控制振盪器為主要研究方向。

在此本論文提出了三種不同的四相位電路。第一個電路是結合倍頻器與push-push VCO所組成的新式四相位電壓控制振盪器，本電路使用了TSMC 0.13µm製程來製作，整體晶片面積為1.03 × 0.914 mm2；在電源供應1V時的功率消耗為3.56mW，而可調頻率電壓範圍為0 ~ 1V，頻率變化為5.43 GHz 至 5.92 GHz；在電路操作於5.5 GHz時偏移1 MHz所測得的相位雜訊為 -117.98 dBc/Hz，FOM為 -187.27 dBc/Hz。
第二個電路採用了改良的尾端串聯式四相位電壓控制振盪器，利用了並聯在尾端串聯晶體的電感來減少電壓的使用，本電路使用了TSMC 0.18µm製程來製作，整體晶片面積為0.512 × 1.065 mm2；在電源供應1.1V時的功率消耗為2.545mW，而可調頻率電壓範圍為 0 ~ 0.6V，頻率變化為 4.38 GHz 至 4.71 GHz；在電路操作於4.4 GHz時偏移1 MHz所測得的相位雜訊為 -120.8 dBc/Hz，FOM為 -189.61 dBc/Hz。

最後一個電路是採用了電感耦合的四相位電壓控制振盪器，利用電感耦合信號注入至尾電流的閘極來產生四相位的輸出，本電路使用了TSMC 0.35µm製程來製作，整體晶片面積為1.084 × 0.938 mm2；在電源供應0.9V時的功率消耗為3.78mW，而可調頻率電壓範圍為0 ~ 0.9V，頻率變化為3.99 GHz 至 4.3 GHz；在電路操作於4.15 GHz時偏移1 MHz所測得的相位雜訊為 -124.61 dBc/Hz，FOM為 -191.18 dBc/Hz。

The recent trend in communication systems is to design all circuit in differential and dividing the signal into I/Q channels. Therefore, QVCO is the most important part of the whole system. The goal of VCO design are low phase-noise and low power consumption. Lower phase-noise is requires to avoid the mixer-converted signal by close interfering tones for VCO circuit. Furthermore, power consumption is another important part in the design of VCO because the lower power consumption could make longer bettery lifetime.

In this thesis describes three different type of quadrature VCO. The first proposed CMOS QVCO combined a frequency doubler and a push-push VCO, which has been implemented with the TSMC in a 0.13μm 1P8M CMOS process and the die area is 1.03 × 0.914 mm2. At the supply voltage of 1.0 V, the total power consumption is 3.56 mW. The free-running frequency of the QVCO is tunable from 5.43 GHz to 5.92 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1MHz frequency offset is -117.98 dBc/Hz at the oscillation frequency of 5.5 GHz and the figure of merit (FOM) of the proposed QVCO is about -187.27 dBc/Hz.

The second circuit used split-source tail inductors. The bottom-series coupling transistors are in parallel with the tail inductors and require no dc voltage headroom. The proposed CMOS QVCO has been implemented with the TSMC 0.18μm CMOS technology and the die area is 0.512 × 1.065 mm2. At the supply voltage of 1.1 V, the total power consumption is 2.545mW. The free-running frequency of the QVCO is tunable from 4.38 GHz to 4.71 GHz as the tuning voltage is varied from 0.0 V to 0.6 V. The measured phase noise at 1MHz frequency offset is -120.8dBc/Hz at the oscillation frequency of 4.4 GHz and the figure of merit (FOM) of the proposed QVCO is about -189.61dBc/Hz.

Finally, a low phase noise quadrature voltage-controlled oscillator (QVCO) was proposed. The circuit used switched tail MOSFET to connect the source of each cross-coupled transistor. Two transformers are used to couple the VCO outputs to the gates of tails. The proposed CMOS QVCO has been implemented with the TSMC 0.35μm CMOS technology and the die area is 1.084 × 0.938 mm2. At the supply voltage of 0.9 V, the total power consumption is 3.78 mW. The free-running frequency of the QVCO is tunable from 3.99 GHz to 4.3 GHz as the tuning voltage is varied from 0.0 V to 0.9 V. The measured phase noise at 1MHz frequency offset is -124.61dBc/Hz at the oscillation frequency of 4.15 GHz and the figure of merit (FOM) of the proposed QVCO is about -191.18dBc/Hz.

中文摘要I
AbstractIII
誌謝V
Table of ContentsVI
List of FiguresVIII
List of TablesXI
CHAPTER 1 INTRODUCTION1
1.1 BACKGROUND1
1.2 THESIS ORGANIZATION4
CHAPTER 2 OVERVIEWS OF  VOLTAGE-CONTROLLED OSCILLATORS5
2.1 BACKGROUND5
2.2 THE OSCILLATOR THEORY5
2.3 COMPONENTS9
2.3.1 INDUCTORS AND TRANSFORMERS9
2.3.2 CAPACITORS AND VARACTORS25
2.3.3 RESISTORS32
2.4 SORTS OF OSCILLATORS33
2.4.1 RESONATORLESS OSCILLATORS34
2.4.2 LC-TANK OSCILLATORS36
2.5 DESIGN CONCEPTS OF VOLTAGE-CONTROLLED OSCILLATORS38
2.5.1 VCO CHARACTERISTIC PARAMETERS40
2.5.2 PHASE NOISE IN OSCILLATOR42
2.5.3 PARALLEL RLC TANK50
2.5.4 QUALITY FACTOR51
2.6 QUADRATURE CMOS VCOS54
2.6.1 TRADITIONAL DESIGN OF QUADRATURE CMOS VCO56
CHAPTER 3 A LOW VOLTAGE QUADRATURE VCO IMPLEMENTED WITH SERIES FREQUENCY DOUBLERS61
3.1 INTRODUCTION61
3.2 CIRCUIT DESIGN63
3.3 DESIGN OF THE TRANSFORMER65
3.4 MEASUREMENT RESULTS66
CHAPTER 4 A LOW VOLTAGE AND LOW POWER BOTTOM-SERIES COUPLED QUADRATURE VCO72
4.1 INTRODUCTION72
4.2 CIRCUIT DESIGN74
4.4 MEASUREMENT RESULTS78
CHAPTER 5 A LOW-PHASE NOISE QUADRATURE VCO USING TRANSFORMER COUPLING AND SWITCHED RESISTOR83
5.1 INTRODUCTION83
5.2 CIRCUIT DESIGN85
5.3 DESIGN OF THE TRANSFORMER87
5.4 MEASUREMENT RESULTS88
CHAPTER 6 CONCLUSION94
REFERENCES96

                                

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