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| 研究生： |
陳鶴仁 Ho-jen Chen |
|---|---|
| 論文名稱： |
SOPC-based演算處理器驗證系統之硬體設計 Hardware Design of a SOPC-based Verification System for Algorithmic Processors |
| 指導教授： |
吳乾彌
Chen-Mie Wu |
| 口試委員: |
陳省隆
Hsing-Lung Chen 張勝良 Sheng-Lyang Jang 陳漢宗 Hann-Trong Chen |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
| 論文出版年： | 2006 |
| 畢業學年度： | 95 |
| 語文別： | 中文 |
| 論文頁數： | 84 |
| 中文關鍵詞： | 嵌入式系統 、演算法 、演算處理器 、硬體設計 |
| 外文關鍵詞： | hardware |
| 相關次數： | 點閱：126 下載：1 |
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本論文係有關以SOPC為基礎的演算處理器驗證系統之硬體設計，相關研究工作包含四大部分：第一部份為雙FPGA板之聯結介面設計；第二部份為FPGA板上的同步動態隨機存取記憶體與FPGA晶片內部的嵌入式靜態隨機存取記憶體控制器設計；第三部份為演算處理器基本架構設計，其包含了演算處理器硬體、靜態隨機存取記憶體、CPU介面電路、直接記憶體存取控制器與內建自我測試電路等；第四部份為演算處理器驗證系統之相關測試程式與電路設計。
整體而言，本論文係以提供一個演算處理器的設計與發展環境為目標，並以簡易的模組附掛方式，來改善硬體設計與驗證流程之效率。
This thesis is related to the hardware design of a verification system for system-on-a-programmable-chip-based (SOPC-based) algorithmic processors. The research work includes four parts: the first part is to design an interface circuit for connecting the two field-programmable gate array (FPGA) boards. The second part is to design memory controllers for both the synchronous dynamic random-access memory (SDRAM), which is on the FPGA board, and the static random-access memory (SRAM), which is embedded in the FPGA chip. The third part is related to the basic structure design for algorithmic processors. The basic structure consists of algorithmic-processing hardware, SRAM, CPU interface circuit, direct memory access (DMA) controllers, and built-in self-test circuit. The fourth part is to develop the related testing programs and circuits for this algorithmic-processing verification system.
On the whole, the goal of this thesis is to provide an environment for the design and development of algorithmic processors. Meanwhile, through using a simple way to append modules, the efficiency of the hardware design and verification flow is improved.
[1] 洪偉程, SOPC-based微處理器匯流排控制器之設計, 國立台灣科技大學碩士學位論文, 民國九十四年。
[2] 林傳傑, 基於JTAG之同步動態記憶體測試系統的設計與實作, 國立台灣科技大學碩士學位論文, 民國九十一年。
[3] 簡弘倫, Verilog晶片設計, 文魁, 民國九十四年。
[4] Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice-Hall, 2003
[5] Janick Bergeron, Writing Testbenches: Functional Verification of HDL Model, 2nd edition, Kluwer Academic, 2003.
[6] Thomas & Moorby’s, The Verilog Hardware Description Language, 5th edition, Kluwer academic, 2002.
[7] IEEE Standard Test Access Port and Boundary-Scan Architecture, Institute of Electrical and Electronics Engineers, Inc., 2001.
[8] Nios II Processor Refrence Handbook, Altera Corporation, 2005.
[9] Quartus II Handbook, Altera Corporation, 2005.
[10] Nios II Software Developer’s Handbook, Altera Corporation, 2005.
[11] Avalon Bus Specification Reference Manual, Altera Corporation, 2005.
[12] ModelSim SE User’s Manual, version 5.8b, Model Technology, 2003.
[13] David A. Patterson & John L. Hennessy, Computer Organization & Design the Hardware/Software Interface, 2nd ed., Morgan Kaufmann, 2003.
[14] IEEE Computer Society, IEEE Standard 1364.1TM-2002, IEEE Standard for Verilog Register Transfer Level Synthesis.
[15] 128M bits Synchronous DRAM datasheet, Micron, Inc., 2003.
[16] StratixII Device Handbook, Altera Corporation., 2005.
[17]Interfacing to Mobile SDRAM with CoolRunner-II CPLDs, Xilinx Corporation., 2004.
