由於矽廣泛地被應用於微電子產業，絕緣層覆矽(SOI)平台不僅可成為低功率消耗及高速度特性之光學與電子學應用的共通基板，而且也被證明可與互補式金屬氧化物半導體(CMOS）的標準製程相容。相對於傳統的二氧化矽波導，擁有高折射係數差異的絕緣層覆矽結構，可以更進一步微小化光波導及以其為主次系統的體積。因此絕緣層覆矽波導是未來低成本與高量產製造光積體電路建構模組(Building Blocks)的最佳選項。

在本篇論文中，將完整地討論與說明矽線波導(silicon wire waveguide)的設計及其0.35-μm CMOS製程的研發。根據商用軟體BeamPROP中的模態分析，我們將完整有系統地將矽線波導幾何形狀的差異對單模態的關係作理論分析與計算。影響矽線波導光學特性的因素，包括與傳統光纖的耦光效率、彎曲半徑、逸漏式模態（leaky mode）及側壁粗糙度散射。根據有限時域差分法（FDTD），我們的模擬計算結果可歸納為: 0.5-μm波導寬度，3-μm彎曲半徑，2-μm SOI埋藏氧化層厚度，及低於2-nm的側壁粗操度可以達到2 dB/cm的光損耗。為了減少波導與光纖之間的耦合損耗，nanotaper亦運用FDTD演算法來設計，尖端寬度為0.12-μm與長度為40-μm可以將模態不匹配損耗降低至0.766dB。我們在國家奈米元件實驗室也以0.35-μm CMOS製程相容之步驟來製作矽線波導。以硬質罩幕進行乾式蝕刻可以成功降低側壁粗糙度，實驗設計低應力的二氧化矽及乾式蝕刻的品質，更可以用於光學與電子電路整合在一個SOI晶片大小並降低成本。

Because silicon is extensively utilized in the microelectronics industry, silicon-on-insulator (SOI) platforms, being the common substrate for both optical and electronic applications and demonstrating the compatibility with standard complementary metal-oxide-semiconductor (CMOS) processing besides low power consumption and high speed performance, become the most popular substrates. As opposed to conventional SiO2 guided on silicon substrate, the SOI structures can be further utilized as the exceptionally high index contrast for ultra-compact optical waveguides and their based subsystems. Therefore, SOI is a promising candidate to construct the building blocks for future photonic integrated circuits using a cost-effective and high-yield process.

In this thesis, the silicon wire waveguide was fully studied and demonstrated in the design and its 0.35-μm CMOS process development. According to the mode solver built in the BeamPROP commercial software, the critical dimensions for silicon wire geometric variations were simulated to be controlled in the single mode region. Followed by finite-difference time-domain (FDTD), the key parameters for optical performance of silicon wire waveguides were theoretically illustrated on the coupling efficiency with traditional fibers, bend radius, leaky modes, and side wall roughness scattering. Our simulation results showed that the bend radius of 3-μm, waveguide width of 0.5-μm, SOI buried oxide layer with 2-μm thickness, and less than 2-nm sidewall roughness could achieve 2 dB/cm optical loss for submicron waveguides. In order to reduce the coupling loss between waveguide and fiber, we utilized FDTD algorithm to design nanotaper, which tip width of 0.12-μm and taper length of 40-μm could minimize the optical mode mismatch down to 0.766dB. Silicon wire waveguide was also fabricated by CMOS compatible process in National Nano Device Laboratories (NDL). Dry etching with oxide hard mask to reduce the sidewall roughness would be demonstrated. Design of experiments for low stress oxide and dry etch quality were also fully developed for highly integrated photonic and electronic circuitry on a SOI chip for size, weight, and cost reduction.

[1] H. Nishihara, M. Haruna, and T. Suhara, “Optical Integrated Circuits” Mcgraw Hill , 1987
[2] K.Okamoto, ”Fundamentals of Optical Waveguide”, Academic Press, 2000
[3] G. T. Reed and A. P. Knights, “Silicon Photonics An Introduction,” John Wiley and Sons, 2004
[4] S. P. Pogossian, L. Vescan, A. Vonsovici, “The single-mode condition for semiconductor rib waveguides with large cross section” Journal of Lightwave Technology, Vol. 16, No. 10, pp. 1851-1853, 1998
[5] A. Yariv and P. Yeh, “Photonics: Optical Electronics in Modern Communications,” Oxford, 2007
[6] G. T. Reed, “Silicon Photonics The State of The Art” John Wiley and Sons, 2008
[7] T. Aalto, “Microphotonic silicon waveguide components” VTT Publications, Vol. 553, 2004
[8] D. V. Thourhout, W. Bogaerts, and P. Dunon, “Submicron silicon strip waveguides” Springer Series in Optical Sciences, Vol. 119, pp. 205-237, 2006
[9] A. Sakai, G. Hara, and T. Baba, “Sharply bent optical waveguide on silicon-on-insulator substrate” Proceedings of SPIE - The International Society for Optical Engineering, Vol. 4283, pp. 610-618, 2001
[10] C. Yuanyuan, Y. Qingfeng, Y. Di, C. Shaowu, and Y. Jinzhong, “Structural optimizations of SOI-based single-mode rib waveguide bends” International Conference on Solid-State and Integrated Circuits Technology Proceedings, Vol. 3, pp. 2015-2017, 2004
[11] Y. A. Vlasov and S. J. McNab, “Losses in Single-Mode Silicon-on-Insulator Strip Waveguides and Bends,” Optics Express, Vol. 12, No. 8, pp. 1622-1631, 2004
[12] H. Yamada, T. Chu, S. Ishida, and Y. Arakawa, “Si photonic wire waveguide devices” IEEE Journal on Selected Topics in Quantum Electronics, Vol. 12, No. 6, pp. 1371-1378, 2006
[13] T. Tsuchizawa, K. Yamada, H. Fukuda, T. Watanabe, J. I. Takahashi, M. Takahashi, T. Shoji, E. Tamechika, S. I. Itabashi, and H. Morita, “Microphotonics devices based on silicon microfabrication technology” IEEE Journal on Selected Topics in Quantum Electronics, Vol. 11, No. 1, pp. 232-239, 2005
[14] F. Grillot, L. Vivien, S. Laval, D. Pascal, and E. Cassan, “Size influence on the propagation loss induced by sidewall roughness in ultrasmall SOI waveguides” IEEE Photonics Technology Letters, Vol. 16, No.7, pp. 1661-1663, 2004
[15] K. K. Lee, D. R. Lim, L. C. Kimerling, J. Shin, and F. Cerrina, “Fabrication of ultralow-loss Si/SiO2 waveguides by roughness reduction” Optics Letters, Vol. 26, No. 23, pp. 1888-1890, 2001
[16] K. K. Lee, D. R. Lim, H. C. Luan, A. Agarwal, J. Foresi, L. and C. Kimerling, “Effect of size and roughness on light transmission in a Si/SiO2 waveguide: Experiments and model” Applied Physics Letters, Vol. 77, No. 11, pp. 1617-1619, 2000
[17] D. K. Sparacin, S. J. Spector, and L. C. Kimerling, “Silicon waveguide sidewall smoothing by wet chemical oxidation” Journal of Lightwave Technology, Vol. 23, No. 8, pp. 2455-2461, 2005
[18] F. P. Payne, and J. P. R. Lacey, “A theoretical analysis of scattering loss from planar optical waveguides” Optical and Quantum Electronics, Vol. 26, No. 10, pp. 977-986, 1994
[19] W. Bogaerts, V. Wiaux, D. Taillaert, S. Beckx, B. Luyssaert, P. Bienstman, and R. Baets, “Fabrication of photonic crystals in silicon-on-insulator using 248-nm deep UV lithography” IEEE Journal on Selected Topics in Quantum Electronics, Vol. 8, No. 4, pp. 928-934, 2002
[20] P. Dumon, W. Bogaerts, V. Wiaux, J. Wouters, S. Beckx, J. V. Campenhout, D. Taillaert, B. Luyssaert, P. Bienstman, D. V. Thourhout, and R. Baets, “Low-loss SOI photonic wires and ring resonators fabricated with deep UV lithography” IEEE Photonics Technology Letters, Vol. 16, No. 5, pp. 1328-1330, 2004
[21] V. R. Almeida, R. R. Panepucci, and M. Lipson, “Nanotaper for compact mode conversion” Optics Letters, Vol. 28, No. 15, pp. 1302-1304, 2003
[22] T. Shoji, T. Tsuchizawa, T. Watanabe, K. Yamada, and H. Morita, “Spot-size converter for low-loss coupling between 0.3-μm-square Si wire waveguides and single-mode fibers” Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting, Vol. 1, pp. 289-290, 2002
[23] T. Tsuchizawa, T. Watanabe, E. Tamechika, T. Shoji, K. Yamada, J. Takahashi, S. Uchiyama, S. Itabashi, and H. Morita, “Fabrication and evaluation of submicron-square Si wire waveguides with spot size converters” Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting, Vol. 1, pp. 287-288, 2002
[24] H. Yoshida, T. Sato, K. Ohira, R. Hashimoto, N. Iizuka, and M. Ezaki, “A novel thin-overcladding spot-size converter for efficient silicon-wire optical interconnections and waveguide circuits” 2008 5th International Conference on Group IV Photonics, GFP, art. No. 4638205, pp. 377-379, 2008
[25] G. Roelkens, P. Dumon, W. Bogaerts, D. Van Thourhout, and R. Baets, “Efficient silicon-on-insulator fiber coupler fabricated using 248-nm-deep UV lithography” IEEE Photonics Technology Letters, Vol. 17, No. 12, pp. 2613-2615, 2005
[26] C. C. Hung, H. C. Lin, and H. C. Shih, “Response surface methodology applied to silicon trench etching in Cl2/HBr/O2 using transformer coupled plasma technique” Solid-State Electronics, Vol. 46, No. 6, pp. 791-795, 2002
[27] W. Bogaerts, R. Baets, P. Dumon, V. Wiaux, S. Beckx, D. Taillaert, B. Luyssaert, J. V. Campenhout, P. Bienstman, and D. V. Thourhout, “Nanophotonic waveguides in silicon-on-insulator fabricated with CMOS technology” Journal of Lightwave Technology, Vol. 23, No. 1, pp. 401-412, 2005
[28] S. K. Selvaraja, P. Jaenen, S. Beckx, W. Bogaert, P. Dumon, D. V. Thourout, and R. Bates, “Silicon nanophotonic wire structures fabricated by 193nm optical lithography” Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting, art. No. 4382268, pp. 48-49, 2007