本論文提出神經網路輔助之區塊循序消除列表(NA-PSCL)解碼器之演算法設計，利用PSCL的區塊解碼特性，與CNN結合，演算法上，減少解碼流程，模擬結果顯示此演算法之效能可接近傳統SCL。
本論文使用Python做為軟體模擬與驗證平台，並利用Xilinx Vivado實現此演算法之硬體設計，使用之FPGA模擬環境為Xilinx Virtex-7 VC707，而設計的電路是以TSMC 40nm CMO實作。
論文內容包含介紹極化碼、傳統SC、SCL、PSCL解碼器介紹、NSC解碼器介紹，演算法模擬與驗證及解碼器硬體架構設計，最後為本論文總結並描述未來展望。

This paper proposes a new algorithm named Neural-Network-Aided Partitioned Successive Cancellation List (NA-PSCL) decoder, utilizing the block decoding chara-cteristic of PSCL and combining CNN Decoder. It could reduce the decoding process in algorithm. Results also show that the algorithm has same performance as traditional SCL algorithm.
We use python as the software simulation and verification platform in this paper, and use Vivado to implement the hardware design of this algorithm. Our FPGA simu-lation environment is Xilinx Virtex-7 VC707, and implement out circuit with TSMC 40nm CMOS.
The paper covers an introduction to polar codes, traditional SC, SCL, PSCL dec-oder introductions, NSC decoder introduction, algorithm simulation and verification, and decoder hardware architecture design. Finally, the paper concludes and provides future prospects.

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