隨著大數據時代的到來，現今的資料處理的數據越來越龐大，多維數據的分析和處理成為各個領域的研究方向。張量是一種多維的數據結構，廣泛應用於信號處理、機器學習、通信系統等領域。其中最受探討的張量相關運算為張量分解。張量分解在許多領域中具有廣泛的應用，如數據分析、訊號處理和圖像處理。張量分解的計算會涉及大量的運算，例如在處理大型數據時，傳統的軟體實現方式可能會造成計算效率低的問題。因此設計高效能的張量分解電路成為重要的研究議題。本文針對張量分解提出電路架構以及改進演算法。本論文首先基於平行化的高階正交迭代演算法，進一步設計電路架構，以達到提升硬體使用率與系統效能的目的。本論文進一步透過提出改進的演算法，並且設計電路進一步改進張量分解電路系統的效能。在基於平行化演算法的張量分解電路架構中，本論文提出共用電路元件來提升硬體用率，並且改變運算過程的順序，提升運算效率。在演算法改進的部分，本論文提出的演算法可以同時更新矩陣，且減少迭帶次數。在電路架構設計上，本論文提出了一種共用硬體電路的張量分解電路架構，提高了硬體的使用率，並且減少了電路面積。本論文基於 FPGA平台進行電路設計與效能評估，並且與先前文獻中的設計有較好的硬體效能改善。

With the advent of the big data era, the amount of data processed today is getting larger and larger, and the analysis and processing of multi-dimensional data has become a research direction in various fields. Tensor is a multi-dimensional data structure, and the most discussed tensor-related operation is tensor decomposition. Tensor decomposition has wide applications in many fields, such as data analysis, signal processing and image processing. The calculation of tensor decomposition involves a large number of operations. Therefore, it is important to design efficient tensor decomposition circuits. This article proposes a circuit architecture and optimization algorithm for tensor decomposition. This paper will conduct circuit design based on a parallelized high-order orthogonal iterative algorithm to improve hardware utilization. In addition, the performance of tensor decomposition is improved by proposing optimized algorithms and designing circuits. In circuit architectures based on parallelization algorithms, shared circuit components are mainly proposed to improve hardware utilization. And change the order of the operation process so that the delay will not be too long and maintain its operation efficiency. In the algorithm optimization part, it is proposed that the matrix can be updated simultaneously and the number of iterations can be reduced. In terms of circuit architecture design, we proposed a tensor decomposition circuit architecture that shares hardware circuits based on the proposed algorithm, which improves the utilization of hardware and reduces the circuit area. This paper reports a performance evaluation based on an FPGA platform, and has better hardware performance than previous designs in the literature.

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