本論文主要係研製微波雷達系統中所需之關鍵零組件。本論文利用傳輸線共振器結構於CMOS, GaAs及GIPD製程中設計多款24 GHz壓控振盪器及24 GHz注入鎖定除三除頻器，另外本論文亦使用源/負載阻抗牽引設計方法，且搭配簡易之輸出、入匹配網路研製一款2.4 GHz高效率F類功率放大器。
本論文研製之壓控振盪器主要係採用駐波振盪器電路架構，並實現於GaAs製程中，且利用T型結構取代傳統均勻傳輸線共振器，以達到微小化且可調之功能。另外，本論文亦使用雙共振腔及分佈式電壓技術研製一型24 GHz CMOS低相位雜訊壓控振盪器，其1 MHz之量測相位雜訊可達-103.27 dBc/Hz。注入鎖定除頻器主要係著重於使用CMOS及GIPD整合製程，並基於駐波壓控振盪器電路架構設計注入鎖定除頻器，其鎖頻相對頻寬可達5 %。功率放大器之研製，則使用諧波源/負載阻抗牽引的方式掃描最佳源/負載阻抗，以設計傳輸線輸出、入匹配網路。本論文所研製之F類功率放大器可獲致76.9 %之效率及39 dBm之輸出功率。

The aim of this thesis is to develop the essential components for microwave radar system applications. For the monolithic microwave integrated circuit (MMIC) design, the transmission line resonators are used to realize several types of 24 GHz voltage control oscillators (VCOs) and divided-by-3 injection locked oscillators (ILFDs) using the CMOS, GaAs and glass integrated passive device (GIPD) processes. Moreover, the high efficiency class-F power amplifier (PA) are also developed in this thesis with the harmonic input and output matching networks, which are designed by source/load pull techniques.
The VCOs are developed based on the architecture of the standing wave oscillator (SWO). The conventional transmission line resonator is replaced by the equivalent T-type structure to miniaturize the circuit size and provide the frequency tuning function. In addition, the dual-tank and distributed voltage techniques are also applied to realize a 24 GHz low phase-noise CMOS VCO with a phase-noise of -103.27 dBc/Hz at 1 MHz offset frequency. Based on the circuit configuration of the SWO structure , the ILFDs are designed using combined CMOS and GIPD process. The relative bandwidth of the simulated locking range is about 5 %. The harmonic source/load-pull technique is utilized to design input and output matching networks of the high efficiency class-F PA with a 76.9 % power added efficiency(PAE) and 39 dBm output power.

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