本篇論文設計一個應用於可攜式生醫系統的類比前端電路(AFE)，電路包含類比前端放大器與類比數位資料轉換器(ADC)，系統以低功耗與低雜訊為設計主軸，所以整體系統功率規格訂定在5u W以下，額定供應電壓1 V；類比前端放大器由三級放大器組成，第一級放大器是利用截波穩定技術消除雜訊，其後兩級則為可調增益的濾波器，使類比放大器輸出振幅符合ADC輸入訊號振幅的要求，在Post-simulation中類比前端放大器共消耗2.4u W，其中截波穩定放大器經修正電容數值後雜訊NEF可達到3以下。ADC解析度10 bit，使用超取樣技術，取樣頻率6.2k Hz，藉以降低ADC雜訊能量，Post-simulation中ADC功率消耗1.6u W，AFE整體系統共消耗4u W。

晶片使用TSMC 0.18um 1P6M製程製作，類比電路使用Full-custom設計，數位電路則使用Verilog設計並用自動合成與自動繞線軟體完成，類比前端放大器的晶片面積包含腳位共 ，ADC晶片面積包含腳位共 ，整體AFE系統晶片面積包含腳位共 。

An analog front-end (AFE) circuit for biomedical system application is proposed. The circuit included both analog front-end amplifier and analog digital converter (ADC). Since the design goals are low power and low noise, system’s power consumption is set to be less than 5 uW and the supply voltage is set to 1 V. The front-end amplifier is composed of a low-noise amplifier (LNA) and a programmable gain amplifier (PGA). The LNA uses the chopper stabilization technique to lower the impact of the flicker noise. The PGA has four gain levels controlled by two bits. The PGA adjusts output voltage of the front-end amplifier to suffice input voltage requirement of the ADC. Post-simulation results show that the power consumption of front-end amplifier is 2.4uW and the NEF of the chopper amplifier is less than 3.By using the oversampling technique, the resolution of the ADC is 10 bits under 6.2k-Hz sampling rate. Post-simulation result shows that the ADC’s power consumption is 1.6u W and the AFE's power consumption is 4u W.

The chip is designed by using TSMC 0.18um 1P6M process. We select Full-custom design to implement the analog circuits of the chip. The digital circuit design follows the cell-based design flow. The chip area of the AFE amplifier is , the chip area of the ADC is , and the chip area of the entire AFE is .

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