本論文主要針對逐次逼近式類比數位轉換器提出兩個研究主題，第一個研究主題為應用於無線生醫監測系統之高速高解析度類比數位轉換器，第二個為應用於生醫感測系統之低功耗類比數位轉換器以及自動增益控制系統。

為了達到高速之需求，第一個研究主題採用直接切換式架構以大幅降低邏輯電路之傳播延遲，且透過提出之自適性迴路延遲控制電路來節省更多的電容陣列切換時間，使單通道之轉換器取樣率可高達50MHz取樣率，並藉由冗餘位元技術，使轉換器在高速運作下仍具有些許容錯能力，使晶片更加穩固。而由於高速運作，為避免轉換器之參考電壓因打線及電路板走線之大電感而導致震盪，參考電壓緩衝器電路亦實現於晶片上。

在生醫感測領域中，低功耗設計為主要考量，而為了最小化轉換器功耗並保持足夠速度，第二個研究主題採用了全電容式輸入訊號衰減技術，將前級放大器之輸出訊號控制在轉換器之滿量程範圍內，使得轉換器之操作電壓可以被單獨提供，不必依賴於類比前端感測電路。而為了能順利推動轉換器，前級放大器之設計方式亦為重要考量，本論文提出之前級放大器為基於透過懸浮閘電晶體技術進行設計，藉由懸浮閘類比編程技術來改變放大器內部電晶體之操作特性，因此可針對於不同應用時，進行電路效能最佳化。而內部電路設計為採用AB類放大器架構，以大幅提升放大器之驅動能力及電源轉換效率，同時，還具有良好線性度。對於生醫應用而言，不同種類生理訊號之振幅差異甚大，為了確保轉換器擁有足夠信噪比，我們亦提出一數位式自動增益控制系統，藉由觀察轉換器之輸出結果，判斷當前訊號振幅大小，並透過迴授控制來調整前級放大器之增益，以最大化轉換器之信噪比，另外，採用自動增益控制系統還能避免設計高解析度轉換器之需求。

第一個設計為透過聯電55nm低功耗互補式金氧半導體製程實現一十二位元以及供應電壓為1.2伏之類比數位轉換器，於每秒五千萬次取樣率及輸入奈奎斯頻率時之模擬之總消耗功率為0.79毫瓦，SFDR為87.45dB，等效電源轉換效率為7.46fJ/conversion-step。第二個設計為採用台積電0.35um 2P4M 互補式金氧半導體製程，實現三個類比數位轉換器以及一自動增益控制系統，前兩個轉換器設計目的為驗證自製電容之線性度，而設計之單位容值分別設計為2.35fF及1fF，第三個轉換器設計目的為降低轉器之功耗，因此採用了輸入衰減技術。量測之前兩個轉換器於每秒二十萬次取樣率及供應電壓為2.5伏時之結果各別為，總功耗為46.7及43.47微瓦、有效位元為9.7及9.65位元、轉換效率為280.7及270fJ/conversion-step。而具輸入衰減技術之轉換器於每秒十萬次取樣率、供應電壓為1.2及2.5V時之量測結果為，總功耗為4.6微瓦、有效位元為9.7位元、轉換效率為54.9fJ/conversion-step。整體而言，此具輸入衰減技術轉換器之電源轉換效率約提升了五倍，而提出之自動增益控制系統之有效位元模擬結果可高達近乎8位元。

然而為了預防未來類比前端感測電路與自動增益控制系統整合腳位不足問題，本論文亦提出一平行輸入轉串列輸出電路，此電路會把轉換器之平行輸出數位碼轉為串列輸出，而量測結果為功能正確。最後，值得注意的是，本論文提出之數位式自動增益控制電路及平行輸入轉串列輸出電路皆採用製程提供之標準數位元件進行設計，以降低設計複雜度。

This thesis presents two research topics for successive-approximation-register analog-to-digital converters(SAR ADCs). The first design is a high speed and high resolution SAR ADC for biomedical wireless monitoring system. The second designs are the low power SAR ADCs and the automatic-gain-control(AGC) system for biomedical sensing front-end system.

For wireless monitoring system, the high speed ADC is required. To achieve high speed, the direct-switching(DS) structure is adopted to increase the speed by reducing the digital prorogation delay , and the proposed adaptive delay controller can further improve the speed. In order to own some error tolerance capability and make the ADC more robust, the redundancy technique is also implemented on the chip.

For biomedical applications, the power consumption the is main design consideration. To minimize the power consumption and maintain enough speed, the capacitive input attenuation(CIA) technique is adopted to attenuate the output signal of the input driver into the full range of ADC. Hence the supply voltage of ADC can be provided individually instead of depending on the analog sensing front end(AFE) chain. To well driver the ADC, the design of input driver is also significant. Based on the floating-gate-MOS(FG-MOS) techniques, the performance of the proposed input driver can be optimized in different applications by programming the FG-MOS. For the amplifier design, the class-AB type amplifier is adopted to increase the driving capability and power efficiency, but also maintaining good linearity. For biomedical sensing system, due to the large dynamic range of biomedical signals, an AGC system is proposed to maximize the signal-to-noise ration(SNR) of ADC by automating control the gain of the input driver.

The first design is a 12-bit DS SAR ADC with 1.2V supply voltage, fabricating by UMC 55nm low power process. At 50MS/s and nyquist input frequency, the DS SAR ADC consumes 0.79mW and achieves the SFDR of 87.45dB from simulation result. The figure-of-merit(FoM) is around 7.46 fJ/conversion-step. The second designs are fabricated TSMC 0.35um 2P4M process with cell-based-design-kit(CBDK). Three SAR ADCs and one AGC system are developed. Two of the SAR ADCs are aiming to verify the linearity of the DACs, both of the DAC's unit capacitor value are 2.35fF and 1fF, respectively. The third ADC design is for reducing the power consumption, therefore, the CIA technique is adopted. Measuring the first two SAR ADCs with 2.5V supply voltage and 200KS/s sampling rate, the power consumption are around 46.7uW and 43.47uW. Reaching the effective-number-of-bit(ENoB) up to 9.7 and 9.65 bits. After calculating, the FoM values are 280.7 and 270 fJ/conversion-step. Measuring the CIA SAR ADC with 100KS/s sampling rate and 1.2V supply voltage. The ENoB can also up 9.7 bits, and the FoM value can be down to 54.9 fJ/conversion-step, which is around five times less than the first two developed SAR ADCs. Moreover, the ENoB of the proposed digital AGC system can also reach around 8 bits from the simulation result.

Last, a parallel-to-serial interface(PSI) circuit is also developed to reduce chip area and save the pin numbers for the integration of AFE chain and AGC system in the future. The PSI function is verified under 2.5V supply voltage.

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