定向自組裝 (directed self-assembly technology) 的技術在10 奈米以
下的導通孔 (contact/via) 的製造上展現了其優勢，為了讓導通孔有
足夠的重疊精度以確保其可製造性，我們限制了導引樣板 (guiding
templates) 的種類，因此也限制了可製造的導通孔格局 (via patterns)
的種類。此外，由於冗餘導通孔插入 (redundant via insertion)可以改
善電路的可靠性及良率，其在電路設計流程上也變成了重要的步驟。
然而，在繞線階段 (routing stage) 如果只單方面考慮冗餘導通孔插
入或是定向自組裝，會使得導通孔的可製造性或是冗餘導通孔插入率
降低。在本論文中，我們率先提出第一個，在細部繞線 (detailed
routing) 時同時考慮到導引樣板及冗餘導通孔插入的可行性。由於不
同的金屬線格局 (wiring patterns) 會導致不同的導通孔格局及不同
的冗餘導通孔候選數量，我們開發出一個精密的繞線圖模型來避免產
生不好的金屬線格局。此外，為了有更佳的導通孔分布及布局的最佳
化，我們也提出了幹線分配 (trunk assignment method) 及一些拔線
重繞 (rip-up and rerouting) 的技術。實驗結果顯示在冗餘導通孔插入
率上，我們的繞線器 (router) 跟目前最新的考慮定向自組裝的細部
繞線器 (DSA-aware detailed router) 比較有著大幅度的改善。

The directed self-assembly (DSA) technology has shown its great potential in via/contact
layer fabrication for sub 10-nm technology nodes. To guarantee sucient overlay
accuracy of generated vias, only a few guiding templates with simple shapes are
feasible, and thus manufacturable via patterns are limited. In addition, redundant
via insertion has become a necessary step in the circuit design ow to improve relia-
bility and yield. However, routing by only considering redundant vias or DSA may
either deteriorate the redundant via insertion rate or damage via manufacturability.
This paper presents the rst work on detailed routing that simultaneously consid-
ers guiding template feasibility and redundant via insertion. Since dierent wiring
patterns result in various via patterns and redundant via candidates, we develop a
sophisticated routing graph model to avoid generating undesired wiring patterns. A
trunk assignment method and several rip-up and rerouting techniques are also pro-
posed for better via planning and layout optimization. Experimental results show
that our router can signicantly improve the redundant via insertion rate compared
to a state-of-the-art DSA-aware detailed router.

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