導通孔在奈米半導體製程中仍然是影響良率的主要原因之一。在積體電路的設計，增加冗餘導通孔(redundant via)是用來解決導通孔失效典型的方法，藉此可同時提高其良率與可靠性。在以元件單位為基礎(cell-based)的設計方式中，在繞線階段所增加雙導通孔是目前有效解決的主流方法，然而雙導通孔需要大量繞線資源。另外，要提升第一層冗餘導通孔插入率(redundant via1 insertion rate)則須藉由標準元件(standard cell)來達成。本篇論文提出一個增強型冗餘導通孔元件檢查及最佳化的方法，運用新式的矩型導通孔(rectangle-via)及藉由自動化的檢查演算方法來提升標準元件庫(standard cell library)的品質，用來改善傳統的雙導通孔(double-via)使用大量繞線資源的問題及提高其低冗餘導通孔插入率的問題。此設計方法可以運用商業軟體來達成，所設計的標準元件庫也適用於目前所有商業的繞線法。ERVLC 不只可使用於多種導通孔(multi-via)的設計中，並且是一個有效的自動化檢查及優化標準元件(standard cell)的工具。實驗結果證實我們設計的標準元件庫不但增加整體冗餘導通孔插入率達13.2％，及達到100%第一層冗餘導通孔插入率。

Via failures are an ongoing challenge in nanometer-scale semiconductor manufacturing processes. Adding redundant vias is the standard method for increasing yield and reliability. Cell-based design approaches are extensively adopted for physical implementation. Standard cells (SCs) increase the rate of redundant via1 insertion in cell-based designs. The conventional method for locating pins and tuning pin geometries is manual. This study proposes an e cient pin layout optimizer that considers various con gurations of redundant vias, such as double-vias and rectangle-vias. The proposed method not only solves the problem of the rate of the redundant via1 insertion, but also provides an e ective pin layout checker and optimizer for designing standard cells. To compare the variability of performance and routability in standard cell libraries, accurate characterizations and routing experiments are provided by commercial simulation and routing tools. Furthermore, the proposed standard cell library is implemented easily in all currently available routers. Compared to the conventional SC library, the experimental results reveal that the proposed library improves the total of inserted double-via and total inserted double-via1 by 9.3% and 19.8%, respectively. The proposed scheme also achieves a 26.3% higher redundant via1 insertion rate than conventional approaches and a 100% rectangle-via1 insertion rate.

[1] J. G. Xi, Improving Yield in RTL-to-GDSII Flows. EE Times, Jul. 11, 2005.
[2] Topology Layout Rule. www.umc.com.
[3] P. Gupta and A. Kahng, \Manufacturing-aware physical design," in Proc.
IEEE/ACM Intl. Conference on Computer-Aided Design, pp. 681{687, 2003.
[4] J. T. Yan, B. Y. Chiang, and Z. W. Chen, \Yield-driven redundant via inser-
tion based on probabilistic via-connection analysis," in ICECS '06. 13th IEEE
International Conference on Electronics, Circuits and Systems, pp. 874 {877,
2006.
[5] K. Y. Lee and T. C. Wang, \Post-routing redundant via insertion for yield/reli-
ability improvement," in Asia and South Paci c Conference, pp. 24{27, 2006.
[6] H. Y. Chen, M. F. Chiang, Y. W. Chang, L. Chen, and B. Han, \Full-chip
routing considering double-via insertion," IEEE Trans. Computer-Aided Design
of Integrated Circuits and Systems, vol. 27, pp. 844 {857, may 2008.
[7] G. Xu, L. D. Huang, D. Pan, and M. Wong, \Redundant-via enhanced maze
routing for yield improvement," in Proceedings of the ASP-DAC, vol. 2, pp. 1148
{ 1151, 2005.
[8] K. McCullen, \Redundant via insertion in restricted topology layouts," in
Proceedings of the 8th International Symposium on Quality Electronic Design,
ISQED '07, (Washington, DC, USA), pp. 821{828, IEEE Computer Society,
2007.
[9] T. Y. Lin, T. H. Lin, H. H. Tung, and R. B. Lin, \Double-via-driven standard
cell library design," in DATE '07 Europe Conference Exhibition, pp. 1 {6, 2007.
[10] T. C. Kan, S. H. Yang, T. F. Chang, and S. J. Ruan, \Design of a practical
nanometer-scale redundant via-aware standard cell library for improved redun-
dant via1 insertion rate," IEEE Trans. on Very Large Scale Integration (VLSI)
Systems, 2011.
[11] T. C. Kan, W. L. Chen, and M. C. Liu, \Integrated Circuit Structure and A
Design Method Thereof, US Patent 7 281 231," 2007.
[12] SiliconSmart. www.magma-da.com.
[13] Synopsys, Mountain View, California, USA, Zroute, IC Compiler, 2010.
[14] Calibre. www.mentor-da.com.
[15] UMC, www.umc.com, L65 SP UM065LSCSPMVBBR Logic and Mixed-Mode
Standard Performance Cell Library, 2010.