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研究生: 阮美貴
My Qui Nguyen
論文名稱: 以現場可程式化閘陣列實現一以RISC-V為基礎之256-bit具動態排程之極長指令處理器
Design and Implementation of a 256-bit RISC-V-based Dynamically Scheduled Very-Long Instruction Word using FPGA
指導教授: 陳伯奇
Poki Chen
林昌鴻
Chang-Hong Lin
口試委員: 陳伯奇
Poki Chen
林昌鴻
Chang-Hong Lin
沈中安
Chung-An Shen
鄭桂忠
Kea-Tiong Tang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 英文
論文頁數: 72
中文關鍵詞: 極長指令RISC-V微處理器動態排程現場可程式化邏輯陣列浮點數
外文關鍵詞: VLIW, RISC-V, Microprocessor, Dynamic scheduling, FPGA implementation, Floating-point
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  • ACKNOWLEDGEMENTS i ABSTRACT ii 摘要 iii CONTENTS iv List of Figures vi List of Tables viii List of Abbreviations ix CHAPTER 1 - INTRODUCTION 1 1.1 Background 1 1.2 Motivation 3 1.3 Contributions 4 1.4 Organization 5 CHAPTER 2 - LITERATURE REVIEW 6 2.1 Commercial products 6 2.2 Academic studies 7 CHAPTER 3 - RISC-V INSTRUCTION SET 13 3.1 Introduction 13 3.2 RV32I: Base Integer 14 3.3 ISA Extensions 15 CHAPTER 4 - PROPOSED VLIW MICROPROCESSOR ARCHITECTURE 20 4.1 VLIW Instruction Format 20 4.2 The entire VLIW architecture 20 CHAPTER 5 - SIMULATION, SYNTHESIS, AND IMPLEMENTATION RESULTS 43 5.1 Functional Verification Results 43 5.2 Instruction per Cycle 45 5.2 Synthesis Results 48 5.3 FPGA Implementation 52 CHAPTER 6 - CONCLUSIONS 56 6.1 General conclusion 56 6.2 Some comments 56 BIBLIOGRAPHY 58

    [1] P. Semiconductors, "An Introduction to Very-Long Instruction Word (VLIW) Computer Architecture," https://web.archive.org/web/20110929113559/http://www.nxp.com/acrobat_download2/other/vliw-wp.pdf.
    [2] R. Olanrewaju, F. F. Eniola, S. B. Junaid, R. Alahudin, F. Anwar and B. Rasool, "Design and Implementation of a Five Stage Pipelining Architecture Simulator for RiSC-16 Instruction Set," Indian Journal of Science and Technology, 2017.
    [3] P. Stravers and J. Hoogerbrugge, "Homogeneous Multiprocessing and the Future of Silicon Design Paradigms," International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers., 2001.
    [4] M. Saldana, D. Nunes, E. Ramalho and P. Chow, "Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI," IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig), 2006.
    [5] M. T. Sim and Q. Yi, "An Adaptive Multitasking Superscalar Processor," IEEE 5th International Conference on Computer and Communications (ICCC), 2019.
    [6] S. S. Omran and A. J. Ibada, "Hardware Implementation of a Two-way Superscalar RISC Processor using FPGA," 1st International Engineering Conference (IEC), Ishik University, 2014.
    [7] A. Waterman, Y. Lee, D. A. Patterson and K. Asanovíc, "The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, Document Version 20191213. [Online]. Available: https://riscv.org/specifications/," Dec. 2019.
    [8] A. D. Souza and P. Rounce, "Dynamically Scheduling VLIW Instructions," Journal of Parallel and Distributed Computing, vol. 60, no. 12, 2000.
    [9] RISC-V GNU Compiler Toolchain, https://github.com/riscv/riscv-gnu-toolchain.
    [10] Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator, https://github.com/westerndigitalcorporation/swerv-ISS.
    [11] J. A. Fisher, "The VLIW Machine: A Multiprocessor for Compiling Scientific Code," Computers, vol. 17, no. 7, pp. 45-53, 1984.
    [12] V. G. Oklobdzija, The Computer Engineering Handbook, Washington, D.C.: CRC Press, 2002.
    [13] STMicroelectronics, "ST200 VLIW Series - ST231 Core and Instruction Set Architecture Manual," http://www.st.com/, 2004.
    [14] F. Sijstermans, "The TriMedia processor: the price-performance challenge for media processing," IEEE International Conference on Multimedia and Expo (ICME), 2001.
    [15] A. Suga and K. Matsunami, "Introducing the FR500 embedded microprocessor," IEEE Micro, vol. 20, no. 4, pp. 21-27, 2000.
    [16] L. Geppert and T. Perry, "Transmeta's magic show [microprocessor chips]," IEEE Spectrum, vol. 37, no. 5, 2000.
    [17] V. O. Kostenko, A. S. Kozhin, N. Y. Polyakov, M. V. Slesarev, V. V. Tikhorskiy and Y. K. Sakhin, "Elbrus-8C: The Latest Yield from MCST and MIPT Collaboration," International Conference on Engineering and Telecommunication (EnT), 2015.
    [18] K.-S. Lin, G. A. Frantz and a. J. R. Simar, "The tms320 family of digital signal processors," http://www.ti.com/lit/an/spra396/spra396.pdf, June 2017.
    [19] L. Nan, X. Yang, X. Zeng, W. Li, Y. Du, Z. Dai and L. Chen, "A VLIW architecture stream cryptographic processor for information security," China Communications, vol. 16, no. 6, pp. 185-199, Jun. 2019.
    [20] A. Bytyn, R. Leupers and G. Ascheid, "An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration," IEEE International Symposium on Circuits and Systems (ISCAS), May 2019.
    [21] C. Iseli and E. Sanchez, "Spyder: A Reconfigurable VLIW Processor using FPGAs," Proceedings IEEE Workshop on FPGAs for Custom Computing Machines, 1993.
    [22] O. Stecklina and M. Methfessel, "A Tiny Scale VLIW Processor for Real-time Constrained Embedded Control Tasks," 17th Euromicro Conference on Digital System Design, 2014.
    [23] C. Pham-Quoc, B. Kieu-Do-Nguyen and A.-V. Dinh-Duc, "Adaptable VLIW processor: The reconfigurable technology approach," International Conference on Advanced Technologies for Communications (ATC), 2017.
    [24] J. A. Fisher, P. Faraboschi and C. Young, Embedded Computing: A VLIW Approach to Architecture, Compilers, and Tools, Morgan Kaufmann, 2004.
    [25] S. Wong, F. Anjam and F. Nadeem, "Dynamically reconfigurable register file for a softcore VLIW processor," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010.
    [26] J. Hoozemans, J. V. Straten and S. Wong, "Using a polymorphic VLIW processor to improve schedulability and performance for mixed-criticality systems," IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2017.
    [27] M. Koester, W. Luk and G. Brown, "A hardware compilation flow for instance-specific VLIW cores," International Conference on Field Programmable Logic and Applications, 2008.
    [28] W. L. Fook, VLIW Microprocessor Hardware Design For ASICs and FPGA, McGraw-Hill, 2008.
    [29] W. W. S. Chu, Dimond RG, S. Perrott, S. P. Seng and W. Luk, "Customisable EPIC processor: architecture and tools," Proceedings Design, Automation and Test in Europe Conference and Exhibition, vol. 3, pp. 236-241, 2004.
    [30] V. Kathail, M. Schlansker and B. R. Rau, "HPL-PD Architecture Specification: Version 1.1, Technical Report HPL-93-80 (R.1)," HP Laboratories, 2000.
    [31] Parallelism, Trimaran: An Infrastructure for Research in Instruction Level, http://www.trimaran.org.
    [32] M. I. Soliman, "A VLIW architecture for executing multi-scalar/vector instructions on unified datapath," Saudi International Electronics, Communications and Photonics Conference, 2013.
    [33] S. Jee and K. Palaniappan, "Dynamically Scheduling VLIW Instructions with Dependency Information," IEEE Proceedings of the Sixth Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT’02), 2002.
    [34] S.-L. Chu, G.-S. Li and a. R.-Q. Liu, "DynaPack: A Dynamic Scheduling Hardware Mechanism for a VLIW Processor," Applied Mathematics & Information Sciences: An International Journal, vol. 6, no. 3, pp. 983-991, 2011.
    [35] M. Technologies, MIPS32 Architecture for Programmers Volume I-III: Introduction to the MIPS32 Architecture, Revision 2.0, 2003.
    [36] S. Wong, T. V. As and G. Brown, "ρ-VEX: A reconfigurable and extensible softcore VLIW processor," International Conference on Field-Programmable Technology, 2008.
    [37] "https://riscv.org/," [Online].
    [38] D. Patterson and A. Waterman, The RISC-V Reader: An Open Architecture Atlas, Strawberry Canyon LLC, 2017.
    [39] D. Patterson, "50 Years of computer architecture: From the mainframe CPU to the domain-specific tpu and the open RISC-V instruction set," IEEE International Solid-State Circuits Conference - (ISSCC), 2018.
    [40] M. Dubois, M. Annavaram and P. Stenstrom, Parallel Computer Organization and Design, Cambridge University Press, 2012.
    [41] N. Takagi, H. Yasuura and S. Yajima, "High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree," IEEE Transactions on Computers , Vols. C-34, no. 9, 1985.
    [42] V. Patil, A. Raveendran, P. M. Sobha, A. D. Selvakumar and D. Vivian, "Out of order floating point coprocessor for RISC V ISA," 19th International Symposium on VLSI Design and Test, 2015.
    [43] Y. Li, Computer Principles and Design in Verilog HDL, Tsinghua University Press, 2015.
    [44] RISC-V GNU Toolchain, riscv-tests, https://github.com/riscv/riscv-tests.
    [45] D. A. Patterson and J. L. Hennessy, Computer Organization and Design, The Hardware/Software Interface, RISC-V Edition, Elsevier, 2018.
    [46] Xilinx, "Xilinx UG364 Virtex-6 FPGA Configurable Logic Block User Guide," 3 February 2012. [Online]. Available: https://www.xilinx.com/support/documentation/user_guides/ug364.pdf.
    [47] Xilinx, "PlanAhead Tutorial: Debugging with ChipScope (UG677)," Xilinx, 20 March 2013. [Online]. Available: https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/PlanAhead_Tutorial_Debugging_w_ChipScope.pdf.
    [48] Xilinx, "Xilinx PG065 LogiCORE IP Clocking Wizard v4.2, Product Guide," 25 July 2012. [Online]. Available: https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v4_2/pg065-clk-wiz.pdf.
    [49] J. P. Shen and M. H. Lipasti, Modern Processor Design, Fundamentals of Superscalar Processors, Waveland Press, 2013.

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