在本論文中，我們設計與實現了一個與ARM v4指令集架構相容的微處理機智財(Intellectual Property, IP)─Proto-ARM9M。由於智財的可重複利用性是建立在智財驗證的完整度上，因此本論文也建立一套完整的測試環境，可用來驗證智財的行為層(behavioral level)、暫存器轉移層(regisiter transfer level)、合成後閘級層(post-synthesized gate level)與佈局後閘級層(post-layout gate level)之設計。
我們根據ARM v4指令集架構的行為描述來設計Proto-ARM9M的行為層模型，並同時設計整個測試環境的架構。在行為層模型驗證成功之後，我們著手暫存器轉移層模型的設計，將5級管線架構的概念導入Proto-ARM9M的資料路徑(data path)中，並針對資料路徑中的指令解碼器(instruction decoder)、暫存器陣列(register file)、移位器(shifter)、算術邏輯單元(arithmetic and logic unit)、乘加器(multiply-accumulator)與程式狀態暫存器(program status register)做特別的設計，以加增加整體效能並減少面積的消耗。暫存器轉移層模型在測試平台的模擬結果與ARM指令集模擬器ADS(ARM Developer Suite)相同，模擬的平均程式涵蓋率(code coverage)可達96.58%。
Proto-ARM9M微處理器智財已分別在Xilinx的Spartan-3 XC3S1500-4FG676 FPGA以及TSMC 0.35 μm元件庫上實現。在FPGA設計部分，消耗了9304個LUT，最高操作頻率為21 MHz，並在實驗板上成功的驗證所有個測試程式。在元件庫方面，核心面積為3420.8 μm × 3212.5 μm，等效閘數(gate count)為55450閘，整體晶片面積則為5251.8 μm × 5087.4 μm，在SS（Slow NMOS Slow PMOS model）模式下操作頻率為33.33 MHz，平均消耗功率為151.2 mW ~ 192.8 mW。

In this thesis, an ARM v4 instruction set architecture compatible microprocessor IP (Intellectual Property), Proto-ARM9M, is proposed. Since the reusability of IP depends on the completeness of its verification, we also develop a test environment to demonstrate IP accuracy on each steps of ASIC design flow, such as behavioral level, register transfer level, post-synthesized gate level, and post-layout gate level model.
Based on the behavior of ARM v4 instruction set architecture, we design the behavioral-level model of Proto-ARM9M, and establish a test environment to verify it. After the behavioral-level model verification is done, we start to design register-transfer-level model of Proto-ARM9M. A typical five-stage pipeline is used in the Proto-ARM9M datapath. The individual module of datapath, such as instruction decoder, register file, shifter, arithmetic and logic unit, multiply-accumulator, and program status register are designed carefully to improve performance and decrease area. The register-transfer-level simulation results in the testbech are the same as ARM instruction simulator, ADS (ARM Developer Suite), and the average code coverage of every module in Proto-ARM9M is 96.58%.
Proto-ARM9M has been implemented and verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.35 μm cell library. In the FPGA part, it takes 9304 LUTs and operates at the maximum working frequency of 21 MHz. Furthermore, all of the testing programs are run successfully in FPGA development board. In the cell-based part, the core occupies 3420.8 μm 3212.5 μm, which is approximately equivalent to 55450 gates, and the whole chip occupies 5251.8 μm 5087.4 μm. Proto-ARM9M consumes about 151.2 mW to 192.8 mW in the SS（Slow NMOS Slow PMOS model）simulation condition at the maximum working frequency of 33 MHz.

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