本論文提出兩個逐次漸進式類比數位轉換器，分別是十八位元每秒五十萬次取樣的逐次漸進式類比數位轉換器使用電容校正技術和二十位元每秒十萬次取樣的逐次漸進式類比數位轉換器使用電容校正技術與殘值超取樣技術。
對於實現高解析度類比數位轉換器而言，面積、功耗、線性度與雜訊的設計具有挑戰。本論文提出的兩個類比數位轉換器皆使用電容橋接陣列的方式降低取樣輸入電容，並使用數位電容校正技術及電容交換技術降低由電容不匹配產生的誤差進而提升線性度。而比較器的雜訊在高解析類比數位轉換器中扮演舉足輕重的角色，往往直接影響類比數位轉換器的解析度，使用靜態前置放大器來抑制比較器所貢獻的雜訊，在二十位元類比數位轉換器中，使用殘值超取樣技術將雜訊進行平均進一步降低雜訊的影響。
本論文提出的十八位元類比數位轉換器在5伏特、 3.3伏特及1.8伏特的操作電壓下，功率消耗為2.486毫瓦。經過電容校正後，量測的訊號對雜訊與失真比是97.4 dB，無雜散動態範圍是111.27 dB，動態範圍103 dB，性能指標是180.4dB。
本論文提出的二十位元類比數位轉換器在5伏特、 3.3伏特及1.8伏特的操作電壓下，功率消耗為2.175毫瓦。經過電容校正後，量測的訊號對雜訊與失真比是107.21 dB，無雜散動態範圍是121.75 dB，性能指標是183.9dB。

This thesis proposed two successive approximation register (SAR) analog-to-digital converters (ADCs). One is an 18-bit SAR ADC with a sampling rate of 500 KS/s employing a capacitor calibration technique and the other is a 20-bit SAR ADC with a sampling rate of 100 KS/s utilizing a capacitor calibration technique along with a residue oversampling technique.
Designing high-resolution ADCs poses challenges in terms of area, power consumption, linearity, and noise. Both ADCs proposed in this thesis utilize a bridge capacitor array to reduce sampling capacitance and employ a digital capacitor calibration technique. The capacitor swapping technique is applied to reduce errors caused by capacitor mismatch and thus enhance linearity. Comparator noise is crucial in high-resolution SAR ADCs, often directly affecting their resolution. To mitigate the noise contributed by comparators, static pre-amplifiers are used. In the 20-bit SAR ADC, the residue oversampling technique is employed to reduce the impact of comparator noise further.
The proposed 18-bit SAR ADC consumes 2.486 mW. It occupies an active area of 0.78 mm2. After capacitor calibration, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are LSB and LSB, respectively. The measured signal-to-noise and distortion ratio (SNDR) is 97.4 dB, signal-to-noise ratio (SNR) is 97.52 dB, dynamic range (DR) is 103 dB, and spur-free dynamic range (SFDR) is 111.7 dB. the equivalent Scherer figure of merit (FOMS) is 180.4 dB.
The proposed 20-bit SAR ADC consumes 2.175 mW. It occupies an active area of 1.1 mm2. After capacitor calibration, the measured SNDR, SNR, and SFDR are 107.21 dB, 107.61 dB, and 121.75 dB, respectively. The simulated FOMS is 183.9 dB.

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