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研究生: 廖建昇
Jian-Sheng Liao
論文名稱: 應用於八倍超取樣D類立體聲放大器之十六位元數位脈衝寬度調變器
16-Bit Dual-Channel Digital Pulse Width Modulator for Hi-Fi Stereo Class-D Audio Amplifier with 8x Oversampling
指導教授: 陳伯奇
Poki Chen
口試委員: 劉深淵
Shen-Iuan Liu
陳怡然
Yi-Jan Chen
李鎮宜
Chen-Yi Lee
陳筱青
Hsiao-Chin Chen
莊英宗
none
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2013
畢業學年度: 101
語文別: 中文
論文頁數: 133
中文關鍵詞: 數位脈衝寬度調變器LED驅動電路D類音頻放大器環形振盪器
外文關鍵詞: Digital pulse width modulator (DPWM), LED driver, Class-D audio amplifier, Ring oscillator
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  • 數位脈衝寬度調變技術(Digital Pulse Width Modulation,DPWM)常見的運用範疇有電源管理IC、馬達轉速控制及LED驅動電路等,近來亦有文獻提出以DPWM概念實現D類音頻放大器。本論文主要目的乃是針對DPWM在Class-D音頻放大器之應用上,依據CD規格及操作頻率與解析度採取適合的設計,提出具雙通道且高精度數位脈衝寬度調變器。透過環形振盪器搭配相位內插器及計數器組成本論文之主要架構,使用此方式,可達到節省面積與成本,且又可進一步提高解析度,又可確保其單調性,以簡單架構獲取極佳效能。
    此數位脈衝寬度調變器是由TSMC 0.18μm 1P6M製程實現電路,供應電壓為1.8V,解析度為16位元,精準度為43.25ps,核心面積僅0.059 mm2,經過量測調幅頻寬為263KHz~418KHz,其操作頻率為352.8KHz時,功耗為39.6mW,INL介於-0.83∼+0.84LSB,可調週期範圍為0~100%,此電路設計確實優於目前其他DPWM電路之設計,具有面積小、高解析度皆為其優越特性。


    The digital pulse width modulation (DPWM) has been widely applied to power management IC, motor speed controller, LED driver, and Class-D amplifier. This thesis presents a dual-channel, high-resolution digital pulse width modulation (DPWM) applicable to Class-D audio amplifiers based on the specifications, operating frequency and resolution for CD audio. The DPWM incorporates ring oscillator along with counter for coarse duty adjustment, phase slection for medium duty adjustment and phase interpolation for fine duty tuning. The major advantages of the proposed structure are low cost, high resolution and monotonicity.
    The proposed DPWM chip is fabricated in a TSMC 0.18μm 1P6M standard CMOS process with a core size of merely 0.059 mm2. It is measured to function well within 263KHz ~ 418KHz operation frequency range. The resolution is 16-bit and the equivalent timing resolution is 43.25ps at 1.8V supply voltage. The power consumption is 39.6mW at 352.8 KHz and the integral nonlinearity is measured to be as small as -0.83~+0.84 LSB. The adjustable duty cycle ranges from 0 to 100%.

    中文摘要 I 英文摘要 II 誌謝 III 目錄 IV 圖目錄 VII 表目錄 XI 第1章 緒論 1 1-1 研究背景 1 1-2 研究動機 2 1-3 系統介紹 4 1-4 論文架構 5 第2章 脈衝寬度調變理論與架構 6 2-1 脈衝寬度調變技術介紹 6 2-2 類比脈衝寬度調變電路 8 2-3 計數器型數位脈衝寬度調變電路 10 2-4 延遲線型數位脈衝寬度調變電路 12 2-5 混合型數位脈衝寬度調變電路 14 2-6 採用數位脈衝寬度調變器優點 16 2-7 脈衝寬度調變電路架構之選擇 18 第3章 功率放大器介紹 19 3-1 傳統功率放大器之介紹 19 3-1-1 A類功率放大器簡介 24 3-1-2 B類功率放大器簡介 27 3-1-3 AB類功率放大器簡介 30 3-1-4 C類功率放大器簡介 32 3-1-5 切換式功率放大器簡介 34 3-2 D類音頻放大器 36 3-2-1 傳統放大器與D類放大器差異 38 3-2-2 D類音頻放大器基本原理 40 3-3 D類音頻放大器主要的失真 43 3-3-1 失真種類 44 3-3-2 利用超取樣技術提高D類音頻放大器之訊雜比 46 3-3-3 利用展頻技術降低電磁干擾 47 第4章 十六位元雙通道數位脈衝寬度調變器 50 4-1 三階可調式之數位脈衝寬度調變器 51 4-2 壓控環型振盪電路 59 4-2-1 環型振盪器 59 4-2-2 差動式環型振盪器 61 4-3 相位內插器 63 4-4 計數器 64 4-4-1 非同步計數器 64 4-4-2 同步計數器 66 4-5 脈衝寬度產生電路 69 4-6 多工器 70 4-6-1 數位式多工器 70 4-6-2 類比式多工器 71 4-6-3 解碼器 72 4-7 數位比較器 73 第5章 電路設計與模擬 76 5-1 設計流程與考量 77 5-1-1 類比區塊設計 77 5-1-2 數位區塊設計 78 5-1-3 混合式設計 79 5-2 類比電路設計與模擬 80 5-2-1 差動式環形振盪器之模擬 80 5-2-2 相位內插器之模擬 85 5-2-3 類比區塊之模擬 86 5-3 數位電路設計與模擬 88 5-3-1 解碼器之模擬 88 5-3-2 計數器之模擬 89 5-3-3 比較器之模擬 90 5-4 整體電路設計與模擬 92 第6章 晶片佈局與量測結果 96 6-1 晶片佈局考量 96 6-2 晶片佈局 98 6-3 晶片量測 100 6-3-1 量測儀器與電路板 100 6-3-2 量測環境建立 103 6-3-3 量測結果 105 第7章 結論與未來展望 113 7-1 結論 113 7-2 未來展望 114 參考文獻 116

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