需要表示與處理巨量數據為機器學習、影像處理和無線通訊等當代重要應用的共同特點。張量為一表示高維度資料的資料結構，因此其在巨量數據的應用中的重要性與日俱增。在與張量相關的訊號處理中，張量分解扮演最為關鍵的角色。張量分解通常應用於系統中對巨量數據進行壓縮及提取關鍵特徵。然而，由於張量的數據資料量龐大與計算複雜度高的特點，設計高效能低複雜度的張量分解處理器為一巨大的挑戰。本論文針對張量分解演算法與積體電路架構進行協同研究探討，設計並實現低延遲及高處理速度的張量分解處理器。具體而言，本論文提出平行高階正交疊代張量分解演算法，以降低張量分解運算中的資料相依性。我們設計的演算法更利用低延遲及高處理速度的張量分解處理器架構設計。本論文也分別基於傳統的高階正交疊代演算法以及我們所提出的平行高階正交疊代演算法，設計張量分解處理器電路架構。在基於傳統演算法的張量分解處理器架構中，我們著重於在運算流程的改善以及資料流程的設計，以降低張量分解運算的延遲。另外，在基於我們所提出的平行演算法的張量分解處理器架構中，我們克服設計提升硬體元件使用效率的積體電路架構，達成以最少的元件達到最大的平行處理程度以及處理速度。本論文的實驗表明，我們提出的低延遲張量塔克分解處理器以約11626999 個邏輯閘的複雜度，實現0.28086 毫秒的延遲。而我們提出的高處理速度張量分解處理器以約13293013 個邏輯閘的複雜度，實現每秒5670 個張量分解的處理速度。與最新文獻中的張量分解處理器相比，我們設計的電路架構提升了60% 的處理速度以及47% 的效率。

Tensor has become an essential data structure to represent high dimensional signals in various applications, such as machine learning, image processing and wireless communications. Among signal processing operations related to tensor, tensor decomposition plays an important role and commonly used to compress and extract critical features from a large number of data in the system. However, due to huge amount of data and highly complicated computations, great challenges for the operation and storage of the tensor decomposition processor are incurred. This thesis aims to design and implement a low-latency and high-throughput tensor decomposition processor through the joint effort of algorithm and VLSI architecture design. Specifically, this thesis presents a parallel higher-order orthogonal iteration (P-HOOI) algorithm. The proposed algorithm overcomes the problem of high data dependence in the iterative operation and leads to a low-latency tensor decomposition data flow. Furthermore, this thesis presents two tensor decomposition processor. To be specific, based on the conventional higher-order orthogonal iteration (HOOI) algorithm, a low-latency tensor decomposition processor is designed and implemented. The experimental results show that this low-latency tensor decomposition processor achieves a latency of 0.28086 m seconds with a complexity of approximately 11626999 gates. Moreover, based on the proposed P-HOOI algorithm, a high-throughput and low-latency tensor decomposition processor is designed and implemented. The data processing flow of this processor is optimized to improve the utilization of each hardware component so that the processing throughput is maximized with a manageable increment of hardware complexity. The proposed high-throughput tensor decomposition processor achieves a throughput of 5670 tensor decomposition per second with a complexity of about 13293013 gates. Compared with the state-of-the-art tensor decomposition processor, the proposed high-throughput decomposition processor achieves a 60% enhancement in throughput and 47% enhancement in efficiency.

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