深次微米製程技術的發展，使硬體持續依照摩爾定律（Moore's Law)成長，處理器與主記憶體之間的速度差距也因此不斷增加。為了縮短兩者之間存在的差距，快取記憶體的設計儼然成為處理器運算速度快慢的關鍵，然而快取記憶體也替整個晶片增加了可觀的功率消耗。在一般嵌入式系統中，快取記憶體的消耗功率佔了相當重的比例。因此，如何有效降低快取記憶體的功率消耗是嵌入式系統設計與未來發展的熱門議題。
在本論文中，我們剖析了傳統快取記憶體設計上的細節，透過觀察及分析處理器存取資料記憶體時產生的行為模式，提出一個低功率資料快取記憶體架構，稱之為部分啟動式路徑預測型快取（partial way-predicting cache）。在此架構中，我們結合了二種技術，標籤記憶體存取忽略與MRU路徑預測型快取記憶體；發展為切換型路徑預測架構，將預測型電路解構成預測（predict）與不預測（non-predict）兩種操作模式，以輔助單元幫助電路決定啟動時機，使電路能具備微量的思考能力，判斷出預測命中（predict-hit）機會較大的情況下才觸發預測。
實驗結果顯示，我們提出的方法能夠有效地降低傳統MRU路徑預測型快取記憶體約76%的效能損失，且達到與傳統路徑預測型快取記憶體相近的低功率效果約43%，並且提供一個AST輔助型電路架構的理念，給往後的研究者以此架構為基礎繼續發展。完成的低功率資料快取記憶體已經與Proto3-ARM9TM、AMBA匯流排與周邊智財整合，並在TSMC 0.18 μm元件庫上實現，其所耗費的核心面積為 1.963 × 1.955 mm2，整體晶片面積為2.501 × 2.497 mm2，在129 MHz操作頻率下，平均功耗為147 mW。

Deep submicron technology leads to the huge growth of hardware as the prediction of Moore's Law. The speed gap between processors and DRAM devices is increasingly widened along the progress of integrated circuit manufactures. To bridge such a gap, the design of cache memory in between the processor and main memory has become critical. However, the addition of cache memory also consumes a lot of power, which is a large part of the total power dissipation of an embedded system. Consequently, the design of a low-power cache memory has become an important issue in an embedded system.
In this thesis, a low-power data cache architecture, called partial way-predicting (assist-trigger) architecture, is proposed. This architecture is based on the improvement of conventional cache architecture according to the access behavior of data cache memory. To explore this, two low-power techniques, the way-predicting cache with MRU table and tag skipping technique, are combined. The resulting cache architecture can be operated in two modes: predict and non-predict. By using an assist unit to trigger the cache system into the prediction mode opportunely, this architecture avoids huge prediction miss effectively.
As compared to conventional 4-way way-predicting cache, the proposed partial way-predicting architecture can reduce about the 76% performance penalty at the cost of 57% power increase. We also provide this AST (assist-trigger) architecture concept for those whom are interested. In addition, the proposed data cache has been integrated with Proto3-ARM9TM, AMBA 2.0 system and related peripherals, designed previously in our lab, and implemented in TSMC 0.18-μm cell library. The resulting Proto3-ARM9TM has a core area of 1.963 × 1.955 mm2 and the whole chip area is 2.501 × 2.497 mm2. The average power consumption is 147 mW at the operating frequency of 129 MHz.

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