由於SoC (System on a Chip)的IC設計漸漸成為業界的主流，因而IC設計的廠商採用DSM (deep sub-micro) 或奈米製程技術來生產所需的產品，因此在設計時，晶片匯流排導線之間所產生的電容及電感串音效應(LC-crosstalk) 對系統效能無論是在功率消耗、訊號延遲、邏輯錯誤及訊號雜訊所產生對訊號完整性及整體系統功率消耗的影響已不容忽視。
隨著晶片製程技術進入奈米（nanometer）紀元，匯流排訊號傳輸的工作頻率已達過Giga 赫茲，同時繞線密度(Routing Density)隨著奈米製程晶片大幅上升，因此訊號傳輸時匯流排導線之間所造成的電容及電感串音效應嚴重影響晶片系統的效能。

因此我們將建立一套同時考量電容及電感串音效應下針對匯流排進行編碼技術的架構，再經由模擬來說明我們採用的編碼技術的方式不但可以達成低功率、低延遲、並且低雜訊。在這方法中我們設計出一個成本評估機制(Cost Function)來針對訊號非反向及反向的形式同時作估算，當資料傳送時先透過此機制估算結果比較非反向及反向的形式的成本(Cost)何者較少，再將之送至匯流排上傳輸。如此在匯流排資料傳輸上我們將可獲得低功率、低延遲、並且低雜訊的結果。此研究的重點是如何在同時考量電容及電感串音效應下設計出一套完整的編碼解碼機制，進而達到低功率、低延遲、並且低雜訊的資料傳輸並且我們所達成的功率延遲雜訊降低能補償成本估算機制所需要編碼解碼電路的額外花費因而得以在兩者之間取得一個平衡相互整合，使得晶片系統無論在效能亦或成本上都能達到最佳化。
實驗結果證實我們所提出的方法可同時降低八位元匯流排的功率消耗、訊號雜訊、延遲可達到19.97%、14.73%、以及17.70%，即使當匯流排寬度增加至三十二位元或六十四位元，我們的方法仍維持顯著的效能。

In this paper, we propose a new bus encoding technique
which simultaneously reduce power, noise, and delay according to
the differential magnitude in the growth and decline of LC-crosstalk on the bus.
LC-crosstalk incurs considerable power consuming and serious signal integrity problems of interconnects.
When input data is transmitted on the bus, the different signal switching behavior
causes differential influences of LC-crosstalk upon interconnects.
Therefore, bus encoding technique on power, noise, and delay of interconnects is
the essential issue for interconnect optimization.

We devise a quantitative cost function to determine the encoding patterns.
The cost function adopts the priority between capacitive and inductive effects
to adequately quantify and generalize LC-crosstalk into a quantified value.
According to the quantified value, we determine how to encode the input data for LC-crosstalk elimination.
Unlike previous works which only eliminate capacitive or inductive crosstalk separately,
our proposed scheme takes LC-crosstalk into account
and decreases power, noise, and delay at the same time with slight extra hardware overhead.

We adopt an algorithm to generalize the worst case delay transition pattern of different bus widths.
Moreover, we also implemented other methods to compare the worst case delay with our proposed approach.
The simulation results indicate that our proposed method not only reduces power and noise but also
has significant efficiency on signal integrity optimization.
Experimental results show that power, noise, and delay reduction by using our scheme are
up to 19.97\%, 14.73\%, and 17.70\% for an 8-bit bus.
As the bus width extends to 32-bit or even 64-bit,
our proposed method still maintains efficient reduction on power, noise, and delay.

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