動態隨機存取記憶體 (Dynamic Random Access Memory, DRAM) 由於其高密度、使用壽命長與低成本等優點經常被廣泛使用於現代電子產品上，而隨著製程的進步，記憶體的良率(Yield) 與可靠度(Reliability) 都受到了影響，為了維持資料正確所需的刷新動作(Refresh) 對記憶體功率消耗及性能(Performance) 的負擔也越來越嚴重。以往有許多論文探討使用錯誤修正碼技術(ECC) 來保護記憶體或是使用備用元件(Redundancy) 來取代錯誤細胞，但沒有針對各種錯誤的即時辨別與修復的相關研究，為了能更有效的運用各種修復技術來修正錯誤，本論文提出整合高可靠度與低功率消耗之動態隨機存取記憶體設計技術。
本技術結合了適應性區塊刷新技術和錯誤修正碼與硬體冗餘技術，在正常使用下錯誤修正碼偵測到錯誤時，會將編碼字變補寫回記憶體並讀出比較來辨別出硬錯誤，再利用硬體冗餘技術配置的備用位元來修復硬錯誤，資料保留錯誤則是透過等待錯誤所在位置之刷新週期時間過後額外插入的讀取指令來辨別，藉由降低區塊刷新技術所配置的刷新區塊其刷新週期來避免資料保留錯誤重複發生，而錯誤修正碼則能維持其對突發的軟錯誤攻擊之保護能力。
本研究實現了高可靠度及低功耗設計技術的硬體架構，並開發一個模擬器評估本技術於記憶體的修復率和良率，針對可靠度、刷新功率消耗與額外硬體成本也都做了詳細的分析，根據實驗結果，本技術可以顯著地提升記憶體的修復率、良率及可靠度，128Mb的記憶體使用本技術後刷新功耗最多能節省87.16%，而只需付出不超過1% 的硬體成本，為可忽略的程度。

Dynamic Random Access Memory (DRAM) is widely used in most modern electronic systems as main memory because of its high density, longevity, and low cost. As the VLSI technologies keep shrinkage and minimization of devices, the yield and reliability of DRAM has been severely affected due to the occurrences of soft errors and permanent faults. Moreover, the data retention time of DRAM cells is limited by inherent leakage current, temperature spans, and aging effects. In order to prevent from data retention faults, periodic refresh operations which devour energy and degrade system performance are required. Fortunately, there are many techniques proposed for protecting DRAM by using the error correction code (ECC) or replacing faulty cells with redundancies. However, most of previous techniques address different fault models separately. In order to conquer these fault models simultaneously with limited repair resources, integrated highly reliable and low-power design techniques are proposed in this thesis.
The adaptive block-based refresh technique and the hybrid ECC and redundancy techniques are integrated in the integrated techniques. When the memory system is used on-line and executes a read operation, the faulty codeword will be complemented and written back again for discriminating hard errors. Thereafter, spare bits can be used to replace the memory cells with hard errors. In order to distinguish the data retention errors, an extra read operation will be issued after the time duration of the original refresh period for this memory word when it is detected faulty. Then the refresh period of refresh region containing this word will be halved to prevent loss of data. Thereafter, the correction capability of the adopted ECC can be used to protect soft errors.
The corresponding hardware architecture of our technique is also proposed in this thesis. We also develop a simulator to evaluate the repair rate, yield, and the reliability. Hardware overhead and refresh power are analyzed, too. According to experimental results, the proposed technique can improve yield, repair rate, and reliability significantly. Furthermore, the refresh power can be saved up to 87.16% with less than 1% hardware overhead for a 128Mb DRAM.

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