本論文研製一具有高效率及高功率因數之單級原邊回授恆壓輸出LED，透過原邊回授控制，偵測變壓器輔助繞組的電壓訊號來實現輸出穩壓，並固定MOSFET導通時間，使輸入電流追隨輸入電壓波形，讓系統能在外部元件數較少的情況下，獲得良好的效率及功率因數，並藉由SIMetrix/SIMPLIS模擬軟體結合理論分析，驗證電路之可行性。
最後研製出一輸出直流電壓45 V/45 W單級原邊回授恆壓輸出之返馳轉換器，模型電路操作在邊界導通模式與導通模式，具有寬範圍交流輸入電壓90 Vrms～277 Vrms，透過不同的操作模式並限制切換頻率，可以改善輕/重載時的效率，實測方面，在最低交流輸入電壓90 Vrms且輸出滿載時，效率為90.45%，在最高交流輸入電壓為277 Vrms且輸出滿載時，效率為91.91%，在寬範圍交流輸入電壓當中，滿載效率最高可達92.3%，最高功率因數可達0.997，與現有文獻相比，使用本文架構於輸出滿載且輸入電壓為90 Vrms及230 Vrms之功率因數分別比文獻高出0.414及0.51，平均效率相差約0.24%，本論文結合理論分析並提供步驟性的電路設計流程，以利讀者瞭解並設計本文電路架構，縮短系統設計時間。

In this thesis, a single-stage primary feedback constant voltage output LED with high efficiency and high power factor is developed. The output voltage is stabilized by primary feedback control, which detects the voltage signal of the transformer auxiliary winding and fixes the MOSFET on-time to make the input current follow the input voltage waveform, so that the system can obtain good efficiency and power factor with fewer external components and is analyzed by SIMetrix/SIMPLIS simulation software to verify the feasibility of the circuit. SIMetrix/SIMPLIS simulation software is used to validate the feasibility of the circuit.
Finally, a single-stage DC voltage 45 V/45 W constant voltage primary feedback flyback converter is developed. The model circuit is operated in boundary conduction mode and conduction mode with a wide range of AC input voltages from 90 Vrms to 277 Vrms, which improves the efficiency at light/heavy loads through the different operation modes and the limitation of the switching frequency. The efficiency is 90.45% at the lowest AC input voltage of 90 Vrms and full load, 91.91% at the highest AC input voltage of 277 Vrms and full load, and 92.3% at full load over a wide range of AC input voltages with a maximum power factor of 0.997. Compared with the existing literatures, the power factor of the framework is higher than that of the existing literature for the outputs of the full-loaded system at input voltages of 90 Vrms and 230 Vrms, and the power factor of the full-loaded system at outputs of 230 Vrms. Compared with the existing literature, the power factor of the architecture of this thesis is 0.414 and 0.51 higher than that of the literature, and the average efficiency difference is about 0.24%. This thesis concludes the theoretical analysis and provides the step-by-step circuit design flow, which is helpful for readers to understand and design the circuit architecture of this thesis and shorten the system design time.

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