相較於傳統運算架構，隨機運算可以有效的減少硬體電路使用量。隨機運算的基礎是建立在機率學上的集合理論，透過隨機的二元數列進行計算。因此，本篇論文使用隨機運算架構建立一個二維渾沌系統並將其用於影像加密，並討論其可行性。首先，我們設計了一個新的二維超渾沌系統，並透過相圖、分歧圖與李亞普諾夫指數驗證其渾沌特性。接著我們透過模擬退火法找出近似方程式以及其對應的隨機運算邏輯電路，並設計了一套簡易的加密流程。為了將在FPGA上實現加密系統與隨機運算，我們先在Altera-Modelsim上對所有電路元件進行模擬，並針對開發版特性做靜態時序分析以確保電路穩定性。最後我們分析了電路的成本、運算時間與加密安全性。根據Quartus 16.1的生成報告，隨機運算電路架構的元件組成明顯地低於傳統電路架構的20%。但是儘管使用了平行加速運算，隨機運算的高延遲缺點不能完全解決。因此我們對本篇題目的改進方向提出建議。

Stochastic computing (SC) is a lower-cost digital computational architecture than conventional computing. The fundamental of SC is based on the set theory of probability and operates on random binary bit streams. Therefore, this thesis proposes a chaotic signal generator based on stochastic implementation and discusses its feasibility.First, we design a novel two-dimension chaotic map for stochastic computing rule and use the optimization algorithm to find the approximate polynomial solution to the objective function. Then, we combine different types of approximations to form a two-dimension hyperchaotic map. We verify chaotic characteristic of the hyperchaotic map by Lyapunov exponent, bifurcation diagram, and phase portrait. Next, we implement the digital circuit in the on FPGA and design an image encryption algorithm. The usage hardware is Altera DE10 standard, and we develop Verilog HDL and the architecture of stochastic computing by Quartus II Prime 16.1.0. Then, we conduct the RTL simulation and static timing analysis of the designed circuit.We verify the feasibility of stochastic computing architecture by Lyapunov exponents and cost evaluation. The hardware footprint of SC is smaller 20% than conventional computing at least. Moreover, we analyze the security of the encryption by performing histogram analysis, correlation analysis, resistance analysis of differential cryptanalysis, and entropy analysis on multiple ciphertexts. Finally, we propose the future improvement direction for the high latency of SC.

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