使用TSMC 0.18-μm CMOS製程製造針對DTV頻段認知無線電應用並使用雜訊消除技術的400-800 MHz低雜訊放大器。低雜訊放大器使用了前饋雜訊消除技術，從而降低主要級電晶體的雜訊。低雜訊放大器達到最大功率增益17.4 dB在455 MHz以及最小雜訊指數1.35 dB在805 MHz。在1.8 V的電源下，功率消耗為16.81 mW。
藉由雜訊消除技術，使用TSMC 90nm CMOS技術製造設計了2.4 / 5.2 GHz雙頻帶的低雜訊放大器實現於Wi-Fi 6的應用。2.4/5.2 GHz雙頻帶低雜訊放大級的主要級使用了分裂負載電感強化的技術以及源極退化電感。此低雜訊放大器模擬結果實現了14.56 / 12.3 dB的功率增益和1.9 / 1.98 dB的雜訊指數。在1 V的電源下，功率消耗為18.37 mW。此外，輸入阻抗和所需雜訊消除級增益的理論結果與模擬結果一致。

A 400-800 MHz LNA using noise canceling technique is designed and implemented for DTV-band cognitive radio applications, and it is fabricated using TSMC 0.18-μm CMOS technology. A feedforward noise canceling technique is applied to the LNA so that the noise of MOSFETs in the primary stage can be reduced. The LNA achieves the maximum power gain of 17.4 dB at 455 MHz and the minimum noise figure of 1.35 dB at 805 MHz. The power consumption is 16.81 mW from the 1.8-V supply.
With the noise canceling technique, the 2.4/5.2 GHz concurrent band low noise amplifier is designed and implemented for Wi-Fi 6 applications, and it is fabricated using TSMC 90nm CMOS technology. The splitting-load inductive peaking technique and source degeneration are used in the primary stage of the concurrent band LNA. The simulated results of LNA achieve the power gain of 14.56/12.3 dB and the noise figure of 1.9/1.98 dB. The power consumption is 18.37 mW from the 1-V supply. In addition, the theoretical results for input matching and the required gain of noise canceling stage agree with the simulation results.

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