本論文研製一個應用於超寬頻3.1-8 GHz之射頻接收機前端電路。此前端電路包含低雜訊放大器、被動式巴倫以及雙平衡混波器且使用台積電所提供0.18微米互補式金氧半製程以1.8伏特來完成所有晶片與量測。低雜訊放大器以三級放大架構為主，第一級採用反相器技術植入變壓器，可以達到頻寬匹配以及減少晶片面積，第二級為cascode結構，可以消除米勒效應且改善平均順向增益，第三級主要於匹配下一級電路。採用被動式巴倫在於不會消耗功率。雙平衡混波器使用current bleeding技術來提昇轉換增益以及改善線性度。
量測結果顯示最大轉換增益為30.32 dB。最小的雜訊為4.79 dB。輸入返回損耗與輸出返回損耗分別為小於-15.3 dB和-13.3 dB。三階輸入截斷點為-21.4 dBm。LO_RF隔離度與LO_IF隔離度分別為-57dB 以及-27.8 dB。晶片面積包含pad為0.984 mm2。總消耗功率為36.88mW。

In the thesis, the proposed RF receiver front-end circuit for ultra-wideband (UWB) systems operating in 3.1-8.0 GHz frequency range is presented. The proposed RF front-end consists of low-noise amplifier (LNA), passive balun and double-balance mixer and is fabricated in a TSMC 0.18-μm CMOS process with 1.8 V supply voltage. The LNA employs three stages. The first stage uses the inverting technique embedding the symmetric planar transformer to achieve the wideband matching and less chip area. The secondary stage uses the cascode structure to eliminate the Miller effect and improve the isolation. The third stage is mostly used to match the following stage. Using the passive balun can reduce the power dissipation. The double-balance mixer uses the current-bleeding to lift the conversion gain and improve the linearity.
The measured results show a maximum power gain of 30.32 dB, a minimum noise figure (NF) of 4.79 dB, and an input return loss (S11) less than -15.3 dB over the whole frequency range. This circuit also achieves an input-referred third-order intercept point (IIP3) of -21.4dBm. The isolations of LO to RF and LO to IF are less than -57 dB and -27.8, respectively. The chip area including pads is only 0.984 mm2 and power dissipation of 36.88mW.

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