研究生: |
徐昌陽 Chung-yang Hsu |
---|---|
論文名稱: |
ARM v4 指令集架構相容之記憶體管理單元智財設計與驗證 The Design and Verification of an ARM v4 Instruction Set Architecture Compatible Memory-Management-Unit IP |
指導教授: |
林銘波
Ming-Bo Lin |
口試委員: |
陳郁堂
Yie-Tarng Chen 詹景裕 Gene Eu Jan 呂紹偉 Shao-Wei Leu |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2007 |
畢業學年度: | 96 |
語文別: | 中文 |
論文頁數: | 83 |
中文關鍵詞: | 智財 、記憶體管理單元 、虛擬記憶體 、記憶體保護 |
外文關鍵詞: | ARM v4, ARM922T, MMU, Memory protection |
相關次數: | 點閱:296 下載:6 |
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記憶體管理單元,也被稱作分頁記憶體管理單元,是計算機的硬體元件,專門負責處理CPU發出的記憶體存取要求。其功能包括將位址轉換、存取權限查驗與提供記憶體共用。藉著將虛擬記憶體位址轉換成實體記憶體位址,提供硬體支援使作業系統可以管理虛擬記憶體。
在本論文中,我們設計與實現了一個與ARM v4架構相容的記憶體管理單元智財(Intellectual Property, IP)。記憶體管理單元主要是由有限狀態機控制單元(FSM Control Unit)、轉址旁觀緩衝區(Translation Look-aside Buffer)與計算與保護機制模組(Calculation and Protection Module)組成,對外則以AMBA(Advanced Microcontroller Bus Architecture)介面讀取外部記憶體中的轉址表(Translation table)。
目前我們已整合了Proto-ARM9M、記憶體管理單元、快取記憶體系統、系統協同處理器與AMBA匯流排介面於Xilinx的Spartan-3 XC3S1500-4FG676 FPGA以及TSMC 0.18 μm元件庫上實現。FPGA設計驗證部分,共使用了21211個LUTs,最高操作頻率可達11 MHz,並於實驗板上搭配自行開發的測試環境以驗證所有測試程式及功能。元件庫方面,核心面積為3183.26 μm × 3423.08 μm,等效閘數(Gate Count)為481533,整體晶片面積為4088 μm × 4081 μm,在SS模式下操作頻率為40 MHz,平均消耗功率約167.1mW。
MMU, sometimes called “paged memory management unit”(PMMU), is a computer hardware component responsible for handling accesses to memory requested by CPU. Its functions include address translation, access permission checks for instruction and data address, and memory sharing. By translating virtual addresses to physical address, it helps the operating system manage virtual memory with hardware support.
In this thesis, an MMU IP (Intellectual Property) compatible to ARM v4 architecture is proposed. The MMU consists of an FSM(Finite State Machine) Control Unit, TLB(Translation Look-aside Buffer), a calculation and protection module, and an AMBA(Advanced Microcontroller Bus Architecture) Interface to read the translation table in the main memory.
Proto-ARM922, which is combined proto-ARM9M with cache, system co-processor, MMU, and AMBA interface, has been implemented and verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.18 μm cell library. In the FPGA part, it takes 21211 LUTs and operates at the maximum working frequency of 11 MHz. Furthermore, all of the testing programs are run successfully in FPGA development board. In the cell-based part, the core occupies 3183.26 μm × 3423.08 μm, which is approximately equivalent to 481533 gates, and the whole chip occupies 4088 μm × 4081 μm, and in the SS (Slow NMOS Slow PMOS model) simulation condition it operates at the maximum working frequency of 40 MHz, and it comsumes about 167.1 mW.
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[10]林晉禾,ARM v4指令集架構相容之微處理器智財設計與驗證,國立台灣科技大學電子工程研究所,碩士論文,2005。
[11]詹勝祥,AMBA 2.0 之相容匯流排控制器智財設計與驗證,國立台灣科技大學電子工程研究所,碩士論文,2007。
[12]蘇侯斌,ARM922T架構相容之系統協同處理器智財設計與驗證,國立台灣科技大學電子工程所,碩士論文,2007。
[13]王偉臣,ARM922T架構相容之快取記憶體系統智財設計與驗證,國立台灣科技大學電子工程所,碩士論文,2007。