MFTL: 多級單元型快閃記憶體儲存系統設計與實作｜國立臺灣科技大學博碩士論文系統

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研究生：	吳宗憲 TSUNG-HSIEN WU
論文名稱：	MFTL: 多級單元型快閃記憶體儲存系統設計與實作 MFTL: Design and Implementation for Multi-Level Cell Flash Memory Storage Systems
指導教授：	邱舉明 Ge-Ming Chiu 謝仁偉 Jen-Wei Hsieh
口試委員:	郭大維 Tei-Wei Kuo 張立平 Li-Pin Chang
學位類別：	碩士 Master
系所名稱：	電資學院 - 資訊工程系 Department of Computer Science and Information Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	39
中文關鍵詞：	快閃記憶體、快閃記憶體轉換層、多級單元型
外文關鍵詞：	Flash memory, FTL, MLC
相關次數：	點閱：492 下載：12
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上一筆

由於低耗電,非揮發性,高效能,穩定及高可攜性等特性,NAND 型快閃記憶體已成為各種嵌入式系統與消費性電子產品的主要儲存媒介之一.NAND 型快閃記憶體又可區分為單級單元型 (Single-Level Cell,SLC) 快閃記憶體與多級單元型 (Multi-Level Cell,MLC) 快閃記憶體兩種.單級單元型快閃記憶體每個單元只能儲存一個位元 (1 bit) 的資料,而多級單元型快閃記憶體每個單元則能儲存兩個或以上位元 (2 bits) 的資料.由於多級單元型快閃記憶體提供了低價格與高容量的解決方案,使它得以在快閃記憶體的市場上,迅速取得最大的市場佔有率.儘管多級單元型快閃記憶體有上述的優點,它的硬體設計架構同樣也衍生了一些新的限制,而這些限制在大部分的學術研究上都尚未被明確地提及.本論文主要針對這些新的限制,設計了一個多級單元型快閃記憶體轉換層(MLC Flash Translation Layer,MFTL),能夠讓上層的檔案系統不需經過修改,即能存取底層的多級單元型快閃記憶體.這個轉換層是專為多級單元型快閃記憶體所設計,但是同樣也可應用在單級單元型快閃記憶體上.考量到目前大部分的應用,在存取快閃記憶體時,均架構在 FAT 檔案系統之下,本論文也針對 FAT 檔案系統的存取特性,提出了在實作上需要注意的考量以及解決方法.本論文進行了一系列的模擬實驗,來對所提出的方法進行效能評估.為了與其他研究所提出的方法能在公平的基準上進行比較,本論文的實驗採用單級單元型快閃記憶體.實驗結果顯示,我們所提出的方法即使應用在單級單元型快閃記憶體上,同樣能夠取得相當好的效能.

NAND flash memory has gained its popularity in a variety of applications as a storage medium due to its low power consumption,non-volatility, high performance, physical stability,and portability. In particular, MLC (Multi-Level Cell)flash memory, which provides a lower cost and higher density solution, has occupied the largest part of NAND flashmemory market share. However, MLC flash memory also
incurs new constraints which are not addressed in most academic researches. Observing that most of applications access NAND flash memory under FAT file system, this paper designs an MLC Flash Translation Layer (MFTL) for flash memory storage systems which takes new constraints of flash memory and access behaviors of FAT file system into consideration. A series of experiments is conducted to evaluate the performance of the proposed scheme. Our experiment results show that the proposed MFTL outperforms other related works.

Contents
Introduction 2
Preliminary and Related Works 5
1 Architecture of Flash-Memory Storage Systems . . . . . . . . . . . . . . 5
2 FAT File Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 HybridMapping Schemes: BAST and FAST . . . . . . . . . . . . . . . . 8
MFTL: MLC Flash Translation Layer 10
1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Write Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Overview of Update Operation . . . . . . . . . . . . . . . . . . . 14
3.2 Forward Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Backward Updates in BlockMappingMode . . . . . . . . . . . . 16
3.4 Backward Updates in PageMappingMode . . . . . . . . . . . . . 18
4 Read Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Implementation Issues for FAT File Systems 24
1 Decision of Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . 24
2 Revision of PageMapStatus . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 Improvement ofMerge Operation . . . . . . . . . . . . . . . . . . . . . . 26
Performance Evaluation 28
1 PerformanceMetrics and Experiment Setup . . . . . . . . . . . . . . . . 28
2 Impact of Different Configurations . . . . . . . . . . . . . . . . . . . . . . 30
3 Comparison with BAST and FAST . . . . . . . . . . . . . . . . . . . . . 30
3.1 Different Number of Extra Blocks . . . . . . . . . . . . . . . . . . 30
3.2 Erase Counts and Extra PageWrites under Different Flash Memory Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3 Memory Consumption . . . . . . . . . . . . . . . . . . . . . . . . 33
Conclusion .............................. 38

                                

[1] ECMA-107 Volume and File Structure of Disk Cartridges for Information Interchange, identical to ISO/IEC 9293. Technical report, ECMA International, June 1995.

[2] Understanding the Flash Translation Layer (FTL) Specification. Technical report, Intel Corporation, Dec 1998.

[3] Aleph One Company. Yet Another Flash Filing System.

[4] L.-P. Chang and T.-W. Kuo. An Efficient Management Scheme for Large-Scale Flash-Memory Storage Systems. In
ACM Symposium on Applied Computing (SAC), pages 862–868, March 2004.

[5] Y.-H. Chang, J.-W. Hsieh, and T.-W. Kuo. Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design. In ACM/IEEE Design Automation Conference (DAC 2007), pages 212–217, June 2007.

[6] J.-W. Hsieh, Y.-L. Tsai, T.-W. Kuo, and T.-L. Lee. Configurable Flash-Memory Management: Performance Versus Overheads. IEEE Transactions on Computers, 57(11):1571–1583, November 2008.

[7] Intel. Flash Cache Memory Puts Robson in the Middle.

[8] Intel. Software Concerns of Implementing a Resident Flash Disk.

[9] Y. Joo, Y. Choi, C. Park, S. W. Chung, E.-Y. Chung, and N. Chang. Demand Paging for OneNANDTM Flash eXecute-In-Place. pages 229–234. CODES+ISSS, October 2006.

[10] A. Kawaguchi, S. Nishioka, and H. Motoda. A Flash-Memory Based File System. In Proceedings of the 1995 USENIX Technical Conference, pages 155–164, January 1995.

[11] J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho. A Space-Effficient Flash Translation Layer for CompactFlash Systems. In IEEE Transactions on Consumer Electronics, Vol. 48, No. 2, pages 366–375, May 2002.

[12] J.-H. Lee, G.-H. Park, and S.-D. Kim. A New NAND-Type Flash Memory Package with Smart Buffer System for Spatial and Temporal Localities. Journal of Systems Architecture, 51:111–123, 2004.

[13] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song. A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation. In ACM Transactions on Embedded Computing Systems, Vol. 6, No. 3, Article 18, July 2007.

[14] M-Systems. Flash-memory Translation Layer for NAND flash (NFTL), 1998.

[15] C. Park, J. Lim, K. Kwon, J. Lee, and S. L. Min. Compiler-Assisted Demand Paging for Embedded Systems with Flash Memory. pages 114–124. Proceedings of the 4th ACM International Conference on Embedded Software (EMSOFT), September 2004.

[16] C. Park, J. Seo, D. Seo, S. Kim, and B. Kim. Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems. In Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003.

[17] Samsung Electronics. Samsung K9LBG08U0M(v1.0) - 32Gb DDP MLC Data Sheet.

[18] Testmetrix Inc. VTE2100.

[19] D. Woodhouse. JFFS: The Journalling Flash File System. In Ottawa Linux Symposium, 2001.

[20] C.-H. Wu and T.-W. Kuo. An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems.In IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2006), pages 601–606, November 2006.

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