數位脈衝寬度調變技術（Digital Pulse Width Modulation，DPWM）目前運用的範疇有電源管理IC應用、控制馬達轉速及LED驅動電路採用DPWM做為LED趨動電路，近來亦有文獻提出以DPWM概念實現Class-D放大器等電路，故我們更期待未來DPWM之應用愈來愈趨廣泛，可以證明本論文所提出之DPWM的優越價值性。
在參閱DPWM相關文獻後，本論文提出採用脈衝縮減緩衝器式DPWM與先放大再縮減式DPWM，其使用脈衝寬度縮減／放大技術概念實現DPWM，係以簡單創意概念，達到極佳效能。
只採用脈衝縮減緩衝器式DPWM使用脈衝縮減緩衝器組成脈衝縮減延遲線，搭配多工器選擇所需責任週期（Duty Cycle）輸出，在解析度高達12位元時面積小，功耗低，又具有數位自我校正功能，以TSMC 0.18μm 1P6M製程實現電路，晶片核心電路面積0.751mm2，經過量測其操作頻率為97kHz∼2MHz超寬範圍，功耗為1.249mW，INL介於-0.41∼+0.43LSB之間，更可證明其線性度表現極佳，引用數位類比轉換器（Digital-to-Analog Converter， DAC）設計之性能因數（Figure of Merit，FOM）概念來判斷本DPWM之高精準度與寬範圍數位自我校正功能優越性，其FOM高達7626.57，遠超過目前其他DPWM設計。

Two wide operation frequency range and high accurary digital pulse width modulators (DPWM) with digital self-calibration are explored in this thesis. Their most popular applications are the DC-DC converter, LED driver, motor control and class-D amplifier.
High performance 12-bits digital pulse width modulator (DPWM) based on pulse shrinking delay line with extremely first simple structure is proposed in this thesis. By digitally calibrating the amount of delay line pulse shrinking, it can achieve 97 kHz ~ 2 MHz wide range operation frequency and 1.249 mW low power consumption at 1 MHz. Fabricated in a TSMC 0.18-μm 1P6M standard CMOS process, the chip size is 0.751 mm2 only. The duty cycle output integral nonlinearity is measured as excellent as -0.41 ~ +0.43 LSB. With an FOM similar to digital-to-analog Converter’s（DAC）, the proposed circuit owns 7626.57, the best than ever number to ensure its superiority.

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