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研究生: 陳文祺
Wen-Chi Chen
論文名稱: 交流電源零交越點雜訊消除技術研究
Noise Reduction Technique for Zero Crossing Detection
指導教授: 劉益華
Yi-Hua Liu
口試委員: 王順忠
Shun-Chung Wang
謝耀慶
Yao-Ching Hsieh
華志強
Chih-Chiang Hua
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2015
畢業學年度: 103
語文別: 中文
論文頁數: 84
中文關鍵詞: 零交越點偵測雜訊消除
外文關鍵詞: Zero Crossing Detection, Noise Reduction
相關次數: 點閱:260下載:2
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盡可能減少電壓、電流突波及電磁輻射一直是現代電力電子發展的重要課題,在進行交流電源轉換時對於干擾的抑制就更加的重要。當使用電力電子裝置進行交流電源轉換時,對電源零交越點之檢測就成為下一電源週期進行轉換的重要依據。因此,提出一種既經濟且有效的方式進行交流電源零交越點檢測。精確的交流電源零交越點檢測可廣泛的應用於工業上,如馬達驅動器、功率因數修正器及並網型逆變器,要達成與交流電源週期同步的工作狀態,就必須依靠正確的零交越點訊號檢測來達成。零交越點檢測同時也可運用於頻率計算及交流電源相位量測。
微控制器已成為今日電力電子應用的主流,同時可利用微處理器進行程式運算以達成低成本且簡單化的雜訊消除功能。在本論文中提出以程式計算來完成具有低成本且高效率的電源零交越點雜訊檢測方式,此方式即使在高度雜訊的環境下仍然能正確的消除雜訊。在本論文中,首先對程式計算的方式進行說明,再設計相對電路及計算程式以驗證本論文的正確性。本論文採用德州儀器公司所提供之TMS320F28069數位訊號處理器及C語言編寫之作業系統來完成實際驗證的結果,最終量測結果可知交流電源50Hz時,經本論文所提程式計算後輸出頻率誤差最大及最小誤差分別為0.023%及0.002%與傳統週期區間判斷處理方式的3.272%及0.345%相比較,兩者之間的差值為140倍及170倍。於60Hz測試時,本論文處理方式最大及最小誤差分別為0.023%及0.004%與傳統週期區間判斷處理方式的2.029%及0.685%相比較,兩者之間的差值為80倍及170倍。由此比例可知有明顯改善。


One of the many issues with developing modern power electronics applications is to keep the spikes and EMI at a minimum, especially when switching AC mains in and out. Switching mains in and out at the zero crossing point requires a precise way of detecting when the next crossing will be. This raises the need for a cost efficient way to detect the zero crossing points. Accurate detection of true zero crossings is important in many fields of industrial electronics such as motor drives, power factor correctors and grid-integrated inverters, where satisfactory line synchronization requires reliable zero crossing information. Zero crossing detection can also be used for other purposes, such as frequency calculation and relative phase measurement.
Most of today’s power electronics applications are controlled by microcontrollers; this gives the possibility to prevent the noise for zero crossing detection (ZCD) in a simple and cost efficient way. In this thesis, a simple digital signal processing method is proposed for efficient noise reduction in zero crossing detectors. The proposed method is very robust against strong impulsive noise. In this thesis, a systematic design procedure will be described first, test platform and prototyping circuit are then developed later to validate the correctness of the proposed algorithm. In this thesis, the proposed algorithm is realized using TMS320F28069 digital signal controller (DSC) from Texas Instrument Corp. According to the experimental results, the steady state maximum and minimum errors for 50 Hz AC input waveform are 0.023% and the smallest error is 0.002%. Compared to conventional ZCD methods, 3.272% and 0.345%, the difference is 140 and 170 times. The steady state maximum and minimum errors for 60 Hz AC input waveform are 0.023% and the smallest error is 0.004%. Compared to conventional ZCD methods, 2.029% and 0.685%, the difference is 80 and 170 times, respectively.

摘要 I Abstract II 誌謝 IV 目錄 V 圖目錄 VII 表目錄 X 第一章 緒論 1 1.1 前言 1 1.2 研究背景與動機 2 1.3 現有雜訊濾除方式 3 1.4 論文大綱 4 第二章 雜訊消除方式 5 2.1 硬體電路雜訊處理 6 2.2 程式演算雜訊處理的方式 10 2.2.1 平均週期計算方式 10 2.2.2 平移週期訊號點平均週期計算方式 11 2.2.3 週期條件限制判斷方式 11 第三章 市電零點取樣訊號除錯架構與原理 12 3.1發電機的慣性 12 3.2 範例使用圖形 13 3.3零點訊號形態分析 15 3.4真實零點訊號判斷方式 19 3.5雜訊分佈於條件判斷區內問題處理 20 3.6第一訊號為雜訊之序列訊號處理 28 3.7第一訊號為雜訊且位於條件判斷區內之序列訊號處理 29 3.8第一訊號為雜訊且連續雜訊落於條件判斷區內訊號處理 30 第四章 硬體測試電路及韌體架構 27 4.1訊號模擬硬體及DSP電路 27 4.1.1 市電頻率訊號模擬電路 28 4.1.2 模擬雜訊產生電路 29 4.1.3 模擬雜訊訊號調整及混合電路 30 4.1.4 TI DSP TMS320F28069硬體電路 31 4.2 韌體架構及程式 33 4.2.1 基礎中斷時脈產生程式 33 4.2.2 外部訊號擷取中斷程式 33 4.2.3 背景流程控制主程式 36 4.2.4 擷取訊號分析程式 38 4.3程式記憶體指標及矩陣 44 第五章 實驗結果與討論 46 5.1 硬體訊號模擬電路及線上模擬器 46 5.2 硬體訊號模擬電路測試結果 47 5.3 韌體對模擬訊號處理結果 50 5.3.1 CCS記憶體資料及時間軸圖示 51 5.3.2 CaseⅠ︰單週期訊號內包含一點雜訊測試紀錄 52 5.3.3 CaseⅡ︰單週期訊號內包含多點雜訊測試紀錄 54 5.3.4 CaseⅢ︰連續週期訊號內包含多點雜訊測試紀錄 55 5.3.5 CaseⅣ︰訊號第一參考點為雜訊測試紀錄 57 5.4 改變雜訊於市電模擬訊號比例之測試紀錄 58 第六章 結論與未來展望 65 6.1 結論 65 6.2 未來展望 65 參考文獻 67

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