本論文將以Pentacene為主動層的材料，並且分為兩種閘極絕緣層處理的方法，第一種方法是在PVA上用CF4電漿處理，並且再旋轉徒步PVP，以獲得較佳的電特性,先利用SEM量測到PVA厚度的改變，再進行電容的量測，由FTIR以及Contact Angle佐證，電容的不規律提升，是因為C-F鍵的導入取代掉原有的O-H鍵，由極性較大的C-F鍵去提升整體K值，並取再進行AFM量測，得知電漿處理後對薄膜表面的影響，不足以影響電特性，以消出一般對電漿處理後，薄膜粗糙度劣化的疑慮。
首先PVA將不使用有毒性的交聯劑，而是與DI.Water混和，使用實驗室已知的比例PVA: DI.Water = 1:8，隨後配合旋轉塗佈初轉速500 rpm，時間20秒，末轉速3500 rpm，持續時間為40秒，然後放進烤箱，以110°C烘烤90分鐘去除多餘水分得到較佳成膜品質，接著使用不同瓦數CF4電漿在PVA上使用處理，在旋轉塗PVP。接這PVP部分，配製溶液的比例濃度、旋轉塗佈轉速以及加熱交聯溫度，來取得最佳值，比例濃度為PGMEA：PVP：PMCF = 100：10：5.0 (wt%)，旋轉塗佈初轉速500 rpm，時間20秒，末轉速5500 rpm，持續時間為40秒，放入烤箱以180。C加熱交聯90分鐘。透過最大瓦數處理後，可以明顯看到電特性改善較佳的有機薄膜電晶體。
第二種閘極絕緣層處理的方式，則是在SiO2上做表面處理，首先將由熱濕氧過的N-type 矽基板所成長的SiO2至入微波腔體，並且通入氧氣，施予65W的功率，藉此消除表面不利於pentacene成長的O-H鍵，以得到較大的晶格尺寸，以利載子傳輸，此點將由FTIR以及Contact Angle證明O-H鍵結的減少，以及AFM證明五苯環晶格大小的成長，最後再由Stres以及磁滯數據，加以說明表面改善不僅提升特性，同時增加穩電晶體的穩定度。

The emerge of organic thin-film transistors (OTFTs) have provided a path to achieve low cost and less complexity of device fabrication. Among all organic materials, pentacene based OTFT is considered to be the most potential candidate for practical application including flexible displays, large-area chemical sensors for artificial skin applications, and radio-frequency power transmission devices. Additionally, due to the possibility of low cost mass production, it might be able to speed up the elevation of internet of things (IoT).
Generally, the combination of PVP and pentacene is utilized to formed the main structure of OTFTs. However, power consumption of device fabricated with low dielectric constant material has always been our great concern. Basically, two paths are provided to solve this difficulty. one is thickness reduction of dielectric, the other is adoption of high k dielectric. Nevertheless, several issues will be encountered when we proceed these two solutions. For thickness reduction of dielectric, due to the fabrication method of organic thin film (spin coating), density of grain boundaries, defects, and pinholes will increase dramatically and lead to degradation of the device. As for adoption of high k dielectric, the quality of pentacene thin film is strongly affected by the surface states on which pentancene is deposited. This means that specific curing process or surface engineering should be conducted before we deposit pentacene on hydrophilicity material such as PVA. In this study, we selected PVA, an organic high k material, as our gate dielectric since its compatibility of flexible device fabrication. Additionally, we tried to reduce the thickness of PVA without creating defects by CF4 dry etching. In order to eliminate roughness effect produced by plasma damage and the hydrophilicity nature of PVA, another PVP layer was deposited on PVA layer. By doing so, a significant improvement on all electrical properties can be achieved, especially for threshold voltage (-7.4 V), an indicator of power consumption.

The second type of gate insulating layer which is improving SiO2 surface . First, the SiO2 is put into the microwave cavity with Oxygen atmosphere, and 65 W is applied. Power, in order to decrease the surface of the OH bond that is not conducive to the growth of pentacene, so that we can obtain a larger grain size for carrier transport, which will prove the reduction of OH bond by FTIR and contact angle.AFM measurement proves larger grain size,so that we can explain Stres and hysteresis data, shows the surface improvement not only enhances the characteristics, but also increases the stability of the device.

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