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研究生: 楊東霖
Dong-Lin Yang
論文名稱: Multi-Channel Architecture-based FTL for Reliable and High-Performance SSD
Multi-Channel Architecture-based FTL for Reliable and High-Performance SSD
指導教授: 謝仁偉
Jen-Wei Hsieh
口試委員: 張立平
none
楊佳玲
none
陳雅淑
none
學位類別: 碩士
Master
系所名稱: 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 英文
論文頁數: 48
中文關鍵詞: SSDPFTLPARPPerformance
外文關鍵詞: SSD, PFTL, PARP, Performance
相關次數: 點閱:173下載:5
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  • Several excellent researches have been proposed to improve the performance of
    solid state drives (SSDs) by exploiting I/O parallelism of multi-channel architecture. However, these researches do not fully explore the internal parallelism and do not take wear leveling into consideration. In this paper, I/O performance is further improved by interleaving request in channel level and striping request in plane level. A wear-leveling-aware distributed garbage collector is proposed to improve SSD lifetime and reclamation efficiency. To balance the utilization of user space among all channels, data migration is performed implicitly during channel selection and explicitly during garbage collection. To the best of our knowledge, this is the first paper on the design of distributed garbage collector for multi-channel flash-memory storage system. The experimental results showed that the proposed scheme can achieve perfect wear leveling and improve the overall performance by 25% for the Windows workload, 23% for the Linux workload, and 42% for the multimedia workload, compared with the related work.


    Several excellent researches have been proposed to improve the performance of
    solid state drives (SSDs) by exploiting I/O parallelism of multi-channel architecture. However, these researches do not fully explore the internal parallelism and do not take wear leveling into consideration. In this paper, I/O performance is further improved by interleaving request in channel level and striping request in plane level. A wear-leveling-aware distributed garbage collector is proposed to improve SSD lifetime and reclamation efficiency. To balance the utilization of user space among all channels, data migration is performed implicitly during channel selection and explicitly during garbage collection. To the best of our knowledge, this is the first paper on the design of distributed garbage collector for multi-channel flash-memory storage system. The experimental results showed that the proposed scheme can achieve perfect wear leveling and improve the overall performance by 25% for the Windows workload, 23% for the Linux workload, and 42% for the multimedia workload, compared with the related work.

    1 Introduction 2 Background 3 PFTL: Parallelism-Aware FTL 3.1 System Architecture 3.2 Dynamic Parallelism Manager 3.3 Distributed Garbage Collector 3.3.1 Garbage Collector: Global vs. Distributed 3.3.2 The Design of Distributed Garbage Collector 3.3.3 Configuration of GC Thresholds 4 Performance Evaluation 4.1 Experimental Setup 4.2 Performance Evaluation for Dynamic Parallelism Manager 4.2.1 Two-Plane Write Commands and Dummy Page Writes 4.2.2 Write Response Time and Read Response Time 4.3 Performance Evaluation for Distributed Garbage Collector 4.3.1 Total Erasures and Erase Response Time 4.3.2 Wear-Leveling 4.4 Overall Performance 4.5 Analysis of Different Channels Number 14.6 Analysis of Parameter 5 Conclusion

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