本論文是有關SOPC-based P1500驗證平台之軟/硬體整合設計與實現，相關研究工作分為以下四大部分：
第一部分為探討IEEE 1149.1與IEEE P1500標準之內容與架構，並在分析TAP與P1500包裝核心之設計架構後，發展出一個P1500驗證平台。
第二部分為設計出記憶體電路與循序邏輯電路等不同功能的核心，以驗證P1500標準可套用在各種類型核心的特性。
第三部分為設計與實現P1500驗證平台之硬體，其中包含了核心鏈選擇指令暫存器、TAP控制器以及核心測試模組中各個不同類型的P1500包裝核心之電路設計，並將以上硬體用SOPC的方式來整合，最後以Altera FPGA開發板實現。
第四部分為使用NIOS II IDE來完成P1500驗證平台之軟/硬體整合設計與實現，其中包含開發相關軟韌體程式、分析電路測試的結果與驗證P1500平台之功能。
整體而言，本論文係以研究P1500驗證平台為目標，並以Altera FPGA開發板實現之。

This thesis is related to the hardware/software codesign and implementation of an SOPC-based P1500 verification platform. The related research work includes the following four parts:
The first part is to study the contents and architectures of IEEE 1149.1 and IEEE P1500 standards. After analyzing the architectures of TAP and P1500 wrapper, a P1500 verification platform is developed.
The second part is to design the cores of different types and features such as RAM and sequential circuits to verify that P1500 standard can be applied to various types of cores.
The third part is to design and implement the hardware of a P1500 verification platform which includes registers for selecting a core chain, a TAP controller and various types of cores surrounded by P1500 wrappers. The hardware mentioned above has been integrated by using the SOPC-based technology and implemented on a development board of Altera FPGA.
The fourth part is related to the hardware/software codesign and implementation of the P1500 verification platform by using the NIOS II IDE. The research includes developing the NIOS II firmware to control the platform, analyzing the testing results from the circuits and verifying the function of the P1500 platform.
On the whole, the goal of this thesis is to do the research on the P1500 verification platform and finally implement it on the Altera FPGA development board.

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