拜現今科學所賜，視訊影像的技術已越來越先進，隨著影像尺寸的變大，處理影像的複雜度也越來越高，單靠網路的傳輸速度已無法負荷影像的傳輸，有鑒於此，影像壓縮的技術變的越來越重要。
本篇論文實現了一個基於超大型積體電路實現高效能高吞吐量之高效率影像編碼標準中去區塊化濾波器架構。在此設計中，我們使用提出了新穎的資料架構及記憶體讀寫的排程來減少記憶體的排線寬度及增進效率。
在接下來的文章中，我們將詳細的介紹我們的濾波器的硬體架構及資料存取的策略。本設計是在台積電90奈米製程的環境下實現，post-layout 的實驗結果顯示，在100MHz的頻率之下，本濾波器可以處理4096 × 2048 像數 (Ultra HD resolution)達每秒60張以上。與其它能達此吞吐量的濾波器相比較，我們能使用更少的邏輯閘數及記憶體達到此效能。

This thesis presents the VLSI architecture and hardware implementation of a high throughput deblocking filter for High Efficiency Video Coding (HEVC) systems. In particular, in order to reduce required memory bandwidth and to improve timing efficiency, novel data structures and memory access schemes for image pixels are utilized in this design.The detailed storage structure and data access scheme will be illustrated and VLSI architecture for the deblocking filter engine will be depicted in this thesis. In addition, the proposed deblocking filter is designed and implemented using TSMC 90nm standard cell library. Experimental results based on post-layout estimations show that the proposed design can achieve 60 frames per second for frame resolution of 4096 × 2048 pixels (Ultra HD resolution) assuming an operating frequency of 100MHz. Moreover, comparing to prior arts targeting on similar performance specifications, the proposed design occupies significantly less logic circuits and SRAMs.

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