研究生: |
曾珊儀 Shan-I Tseng |
---|---|
論文名稱: |
以FPGA設計與實現之全數位式鎖相迴路 The Design and Implementation of an All-Digital Phase-Locked Loop on FPGA |
指導教授: |
林銘波
Ming-Bo Lin |
口試委員: |
林昌鴻
Chang Hong Lin 陳郁堂 Yie-Tarng Chen |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2019 |
畢業學年度: | 107 |
語文別: | 中文 |
論文頁數: | 58 |
中文關鍵詞: | 全數位式鎖相迴路 、時脈產生器 、快速鎖定 、現場可程式邏輯陣列 、低成本 、小面積 |
外文關鍵詞: | ADPLL, all-digital phase-locked loop, fast-lock-in, clock generator, FPGA, small-area |
相關次數: | 點閱:796 下載:0 |
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許多附有快速鎖定功能全數位式鎖相迴路(all-digital phase-locked loop)在過去被提出,但往往都是花大面積與高功耗去達成。而在終端裝置應用中,要求嵌入式系統低功率和低成本,但也需要快速鎖定功,以便微控制器可以從睡眠模式快速喚醒。
本論文提出了一個適用於微控制器之時脈產生器全數位式鎖相迴路。一個由多工器鏈組成的數位控制振盪器(digitally controlled oscillator)設計為兩種模式:振盪模式和時間數位轉換模式。因此,DCO可在一開始時用來量測輸入頻率,改善鎖定時間,之後再作為振盪器運作。藉由重複利用延遲線,此全數位式鎖相迴路可以以較小的面積實現更快的鎖定時間。本論文也提出了依FPGA架構特性所實現之細調延遲單元,最高可在FPGA上達到0.137 ns解析度。
本論文提出全數位式鎖相迴路在Xilinx Virtex-5 V5LX110T上實現,使用LUTs(lookup table) 471個、暫存器179個,輸出範圍為8.22MHz-78MHz,可在十個週期內進入鎖定狀態。輸出頻率為75 MHz時,峰峰值抖動為0.154ns。
A lot of fast-lock-in all-digital phase-locked loops (ADPLL) have been proposed, but they usually come with large area cost and power consumption. For those low-end sensor devices, low-power and low-cost ADPLLs are required. A fast-lock-in feature is also desired so that microcontroller can wake up quickly from sleep mode to run mode.
In this thesis, a complete all-digital phase-locked loop for clock generation is proposed. A multiplexer-chain-based digitally controlled oscillator (DCO) is designed into two modes: the oscillating mode and the time-to-digital conversion (TDC) mode.
Hence the DCO can be used to capture the input frequency at the beginning to improve lock-in time and then work as oscillator later. As a consequence, the ADPLL can achieve faster lock-in time at a small cost by reusing the delay line. This thesis also proposes a fine-tuning delay cell made of FPGA primitives in which it can achieve 0.137-ns resolution on FPGA.
The proposed ADPLL is implemented on Xilinx Virtex-5 V5LX110T. It uses 471 LUTs and 179 registers. The ADPLL output range is from 8.22 MHz to 78 MHz and can enter lock-in status within ten cycles. The peak-to-peak jitter is 0.154 ns with the output frequency of 75 MHz.
[1] C.-C. Hung and S.-I. Liu, “A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithm,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 6, pp. 321–325, Jun. 2011.
[2] D. Sheng, C. C. Chung, and C. Y. Lee, "A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications," IEEE APCCAS, pp. 105-108, Dec. 2006.
[3] T. Watanabe and S. Yamauchi, “An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 198–204, Feb. 2003.
[4] C.-T. Wu, W.-C. Shen, W. Wang, and A.-Y. Wu, “A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 6, pp. 430–434, Jun. 2010.
[5] Scaling Ching-Che Chung, Wei-Siang Su, and Chi-Kuang Lo, ”A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency,” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 24, no. 1, pp. 408-412 , Jan. 2016.
[6] 陳逸瑋,一個快速鎖定 460 .1 MHz 至 6.17 7GHz之全數位式鎖相迴路的設計Design of a Fast Lock ing 460.1MHz to 6.1 7 7GHz,國立交通大學電機與控制工程學系碩士論文,中華民國一零一年七月。
[7] Thomas Olsson and Peter Nilsson, “A Digitally Controlled PLL for SoC Applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 5, pp. 751-760, May 2004.
[8] M. Kumm, H. Klingbeil, and P. Zipf, “An FPGABased Linear All-Digital Phase-Locked Loop,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 57, no. 9, pp. 2487-2497, Apr. 2010.
[9] P. Paliwal, P. Laad, M. Sattineni, and S. Gupta, "Tradeoffs between settling time and jitter in phase locked loops", IEEE 56th Int. Midwest Symp. on Circuit and Systems, pp. 746-749, Aug. 2013.
[10] Saeed Golestan, Malek Ramezani, Josep M. Guerrero, Francisco D. Freijedo, and Mohammad Monfared, “Moving Average Filter Based Phase-Locked Loops: Performance Analysis and Design Guidelines,” IEEE Transactions On Power Electronics, vol. 29, no. 6, pp. 2750-2763 , Jun. 2014.
[11] Pao-Lung Chen, Ching-Che Chung, and Chen-Yi Lee, “A Portable Digitally Controlled Oscillator Using Novel Varactors”, IEEE Transactions On Circuits And Systems—Ii: Express Briefs, vol. 52, no. 5, pp. 233–237, May 2005.
[12] C.-C. Chung and C.-Y. Lee , “An All-Digital Phase-Locked Loop for High-Speed Clock Generation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 347-351, Feb. 2003.
[13] C. -T. Wu, W. Wang, I. -C. Wey, and A. -Y Wu, "A scalable DCO design for portable ADPLL designs," IEEE International Symposium on Circuits and Systems, pp. 5449-5452, May 2005.
[14] UG190 Virtex-5 FPGAUser Guide (v5.4), pp. 173-176, March 16, 2012
[15] DS202 Virtex-5 FPGA Data Sheet: DC and Switching Characteristics (v5.5), pp. 44, June 17, 2016.
[16] ChipScope Pro Software and Cores, October 16, 2012.
[17] R. Stefo, J. Schreiter, J. Schlüßler, and R. Schüffny, "High Resolution ADPLL Frequency Synthesizer for FPGA- and ASIC-based Applications," IEEE International Conference on Field-Programmable Technology, pp. 28-34, 2003.
[18] W.-H. Chen, W.-F. Loke, and B. Jung, “A 0.5-V, 440-μW frequency synthesizer for implantable medical devices,” IEEE J. Solid-State Circuits, vol. 47, no. 8, pp. 1896–1907, Aug. 2012.