近年來，複晶矽薄膜電晶體(Poly-Si TFTs)已經廣泛的被應用在不同的產品上，例如：靜態隨機處理記憶體(SRAMs)、光偵測放大器、掃描器、主動式矩陣液晶顯示器(AMLCDs)等，原因在於複晶矽薄膜電晶體比非晶矽薄膜電晶體具有較高的電子移動率(field effect mobility)，進而增進了同時將主動矩陣及周邊驅動電路整合在同一基板上的能力。然而，傳統的自我對準(self-aligned)複晶矽薄膜電晶體在電特性上卻存在了幾個不欲發生的效應，包括短通道效應(Short-channel effect)、閘極引起汲極漏電流效應(gate-induced drain leakage, GIDL)、汲極引發位障降低效應(drain-induced barrier lowering, DIBL)、扭結效應(kink effect)和熱載子效應(Hot-carrier effect)，都會造成電性操作上的不穩定性。這些效應主要是靠近汲極端的大電場所引起。因此，必須降低該電場以改善上述的現象。為了改善元件特性及簡化製程，此論文透過元件結構的改變以及相關參數模擬分析來實踐獲得高性能的薄膜電晶體。
我們將分析具有四種不同汲極結構的薄膜電晶體，包含傳統型薄膜電晶體、輕摻雜型薄膜電晶體(LDD)、大角度離子佈植薄膜電晶體(LATID)以及間隙壁後大角度離子佈植薄膜電晶體(LATIAS)。當通道長度為1.0 μm時，LATID元件因為雜質侵入通道較多，產生了汲極與源極間的貫穿效應。然而，LATID結構藉著較平緩的濃度分佈，能夠降低電場的大小。我們可以藉由通道摻雜的方式來搭配LATID元件，在不增加電場的情形下，抑制住貫穿效應。因此，在元件尺寸為1.0 μm時，LATID結構搭配通道摻雜，比起傳統型薄膜電晶體以及輕摻雜型薄膜電晶體，有著較小的漏電流。
當我們將通道長度進一步的微縮到0.5 μm時，LATID結構產生了非常嚴重的貫穿效應，即使這時使用通道摻雜，仍然沒有太好的改善。藉由間隙壁後大角度離子佈植的方式，有效地減輕了雜質侵入通道過深的問題。因此，元件在0.5 μm時，LATIAS的結構可以產生比傳統型薄膜電晶體以及輕摻雜型薄膜電晶體更小的漏電流。

Polycrystalline silicon thin-film-transistors (Poly-Si TFTs) have been widely used in various applications, such as static random memories (SRAMs), photodetector amplifier, scanner, and active matrix liquid crystal displays (AMLCDs). The electron field mobility of the ploy-Si TFT is larger than that of the amorphous-Si (a-Si) TFT, allowing the integration of both active matrix and driving circuitry on the same substrate. However, the conventional self-aligned poly-si TFT induces several undesired effects in the electrical characteristics, including short-channel effect、GIDL、DIBL、kink effect and hot-carrier effect. These effects are related to the presence of high electric fields at the drain junction. Hence, the relief of the electric field near the drain region is essential. In this study, in order to improve the electrical properties of devices and process simplification, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation.
Four types of TFTs with different drain structures have been examined, including the conventional single source/drain TFT, the lightly-doped- drain (LDD) TFT, the large-angle-tilt-implantation-drain (LATID) TFT, and the large-angle-tilt-implantation-after-spacer (LATIAS) TFT. For a channel length of 1.0 μm, the LATID TFT devices may suffer from source/drain punch-through, due to encroachment of dopant into the channel region. However, the LATID structure can help to reduce the electric field due to a gradual dopant distribution. Accordingly, for the TFT devices with LATID structure, a proper channel doping may be employed to suppress the punch-through without considerably enhancing the electric field near the drain region. As a result, for a channel length of 1.0 μm, the LATID TFT devices with channel doping may cause a much smaller off-state leakage current than the LDD TFT and the concentional TFT devices.
On the other hand, while the device is further scaled down to 0.5 μm, the LATID TFT devices may suffer from serious source/drain punch-through. Even with the usage of channel doping, the off-state leakage is still large. By using an oxide spacer prior to LATID implantation, the dopant encroachment into the channel region may be reduced. As a result, for a channel length of 0.5 μm, the LATIAS TFT device may cause a relatively smaller off-state leakage current than the LDD TFT and the conventional TFT devices.

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