研究生: |
李雅婷 Ya-Ting Li |
---|---|
論文名稱: |
5G 置信度傳播位元翻轉平行化極化解碼器設計與實現 The Design and Implementation of 5G Parallelization Polar Decoder with Belief Propagation and Bit-Flip |
指導教授: |
王煥宗
Huan-Chun Wang |
口試委員: |
王瑞堂
Jui-Tang Wang 林敬舜 ChingShun Lin 王煥宗 Huan-Chun Wang |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2021 |
畢業學年度: | 109 |
語文別: | 中文 |
論文頁數: | 61 |
中文關鍵詞: | 極化碼解碼器 、置信度傳播解碼 、置信度傳播位元翻轉解碼 、一致化因子圖 |
外文關鍵詞: | Polar Code Decoder, Belief Propagation Decoder, BP Bit Flip Decoder, Uniform Factor Graph |
相關次數: | 點閱:343 下載:0 |
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本論文提出應用於5G的極化碼(Polar Code)解碼器,使用置信度傳播演算法,並專注於改善極化碼置信度傳播位元翻轉解碼的高疊代次數帶來的高延遲。超大型積體電路(VLSI)設計與實現,在硬體架構上以降低複雜度、設計不同碼長,以及降低延遲為主要目標,以此提出平行化的流程與架構,能夠以倍數縮減冗長的位元翻轉流程,架構中藉由一致化因子圖(uniform factor graph)來降低設計複雜度。 本論文軟體使用的模擬環境為MATLAB,使用的FPGA模擬環境為Virtex-7 VC707,而設計電路之實現則是使用TSMC 40nm CMOS製程技術進行實作,並且根據[11]的數據為參考。最後將完成的各項數據表現與比對以及未來展望作為本文的結論。
This thesis proposes the design and implementation of Polar Code decoder applied to 5G, with Belief Propagation algorithm, and focuses on improving the high latency caused by the high iteration times of the Polar Code Belief Propagation bit flipping decoding. In the hardware architecture, the purpose of the design is configurable code length 、reduce complexity, and reduce delays. we propose a flow and a structure of parallelized Bit Flip Decoder. It is capable of using a lot fewer iteration while in the Bit Flip part of flow.In the bit flipping process, by uniform factor graph is used in the architecture to reduce design complexity.
The software simulation environment of this thesis is MATLAB, the FPGA verification environment is Virtex-7 VC707, and the realization of the design circuit is implemented by TSMC 40nm CMOS process technology. And according to the data in [11] as a reference .Finally, the completed data performance and comparison and future prospects are the conclusions of this article.
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