使用正端訊號追蹤DAC切換技巧之10-bit 20MS/s差動架構連續漸進式類比數位轉換器晶片設計

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研究生：	謝政谷 Cheng-Ku Hsieh
論文名稱：	使用正端訊號追蹤DAC切換技巧之10-bit 20MS/s差動架構連續漸進式類比數位轉換器晶片設計 The 10-bit 20-MS/s Fully Differential SAR ADC Chip Design Using Positive Input Signal Tracking DAC Switching Method
指導教授：	黃進芳 Jhin-Fang Huang
口試委員:	張勝良 Sheng-Lyang Jang 徐敬文 Ching-Wen Hsue 劉榮宜 Ron-Yi Liu 溫俊瑜 Jiun-yu Wen
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2014
畢業學年度：	102
語文別：	英文
論文頁數：	90
中文關鍵詞：	連續漸進式類比數位轉換器
外文關鍵詞：	SAR ADC
相關次數：	點閱：272 下載：0
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上一筆

本論文中討論以TSMC 1P6M 0.18 μm CMOS製程，實現一個十位元、每秒兩千萬次取樣時間之逐漸逼近式類比數位轉換器。十位元類比數位轉換器中的數位類比轉換器為了有較高的準確度，使用二進位加權電容陣列
，並採用所提出之單端DAC切換技巧來降低切換能量和電容面積，取樣保持電路包含靴帶式電路以提升取樣開關線性度。兩級的動態比較器有較佳的電壓偏移。非同步式控制邏輯可以避免使用額外高速之外部時脈，並有效分配比較周期所需時間。
經由HSPICE和SpectreRF輔助設計軟體驗證，結果在供應電壓為1.8 伏特下，量測差分非線性度及積分非線性度為 1.2 LSB和1.54 LSB。當輸入訊號為10 KHz下，其量測所得有效位元為8.85-bit，本晶片面積包含ESD PADs為0.57 mm2，整體電路功率消耗為910 μW。

This paper presents a 1.8-V 10-bit 20MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in the TSMC 0.18-um CMOS process. By applying a single-sided switching method that reduces DAC switching energy, the proposed SAR ADC achieves lower power consumption. In order to avoid using an external high frequency clock to drive the ADC, asynchronous control logic is used. A pre-amplifier based comparator reduces the kickback noise from the logic circuit. A bootstrapped switch increases the sample linearity of the ADC.

The SAR ADCs were simulated by HSPICE and SpectreRF. The 10-bit ADC was taped out by TSMC. The measured results for differential and integral nonlinearity of the 10-bit ADC are within 1.2/-0.4 LSB (Least Significant Bit) and -1.54~1.1LSB respectively at full sampling rate. The measurement results show an effective number of bits (ENOB) of 8.85-bits with a sampling frequency of 20 MHz at a 10 KHz input frequency. The chip area, including pads, is 0.57 mm2. Power consumption of this ADC is 910μW with a 1.8 V supply voltage.

Abstract(in Chinese)	II
Abstract(in English)	III
Contents	IV
List of Figures	VI
List of Tables	X

CHAPTER 1  Introduction	                                                       1
1  Motivation	                                                               1
2  Focus and Contributions	                                               2
3  Organization of This Thesis	                                       3

CHAPTER 2  Fundamentals of Analog-to-Digital Converter                         4
1  Introduction	                                                       4
2  Basic Concepts	                                                       4
2.1  Differential Nonlinearity (DNL)	                                       4
2.2  Offset Error	                                                       5
2.3  Gain Error	                                                       6
2.4  Missing Codes	                                                       6
2.5  Integral Nonlinearity (INL)	                                       7
2.6  Signal-to-Noise Ratio (SNR)	                                       7
2.7  Signal-to-Noise and Distortions Ratio (SNDR)	                       8
2.8  Spurious Free Dynamic Range(SFDR)	                               8
2.9  Resolution and Effective Number of Bits (ENOB)	                       8
2.10  Coherent Sampling	                                               9
3  Architectures of Analog-to-Digital Converters	                       9
3.1  Flash ADC	                                                       9
3.2  Two-Step Flash ADC	                                              10
3.3  Time-Interleaved ADC	                                              11
3.4  Pipelined ADC	                                                      12
3.5  Successive Approximation ADC	                                      13
3.6  Sigma-Delta ADC	                                                      14
3.7  Conclusion	                                                      15
4  Papers’ Survey	                                                      15
5  Summary	                                                              21
CHAPTER 3  Energy Efficient DAC Switching Method                              22

1  Introduction	                                                      22
2  Conventional SAR ADC	                                              23
3  Proposed SAR ADC	                                                      25
4  Analysis of Switching Energy In DAC Network	                      27
5  Summry	                                                              33
CHAPTER 4  Chip Design of 10-bit 20-MS/s SAR ADC	                      34
1  Introduction	                                                      34
2  The 10-bit 20-MS/s SAR ADC architecture	                              34
3  Circuit Level Design	                                              35
3.1  Sample and Hold Circuit	                                              35
3.2  Comparator	                                                      41
3.2.a  Architecture	                                                      43
3.2.b  Specification	                                                      45
3.2.c  Simulation results	                                              46
3.3  Digital to Analog Converter	                                      48
3.3.a  Charge Redistribution DAC	                                      48
3.3.b  KT/C noise	                                                      50
3.3.c  Capacitor matching	                                              50
3.4.d  Placement of Capacitors	                                      52
3.4  SAR Control Logic Circuit	                                      52
3.4.a  Synchronous SAR Controller	                                      52
3.4.b  Asynchronous SAR Controller	                                      53
3.4.c  Proposed Asynchronous SAR Controller	                              54
3.5  Switching Logic	                                                      56
3.6  Digital Buffer Circuit	                                              56
4  Simulation Results	                                                      59
5  Measurement Results	                                              64
5.1  Measurement Considerations	                                      64
5.2  Chip Floor Plan and PCB Design	                                      65
5.3  Measurement Instruments	                                              67
5.4  Measurement Results	                                              68
6  Conclusions	                                                      71
CHAPTER 5  Conclusions and Future Work	                                      72
1  Conclusions 	                                                      72
2  Future Work	                                                      73
References                                                                    74
Appendix                                                                      76

                                

[1] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol 45, no. 4, pp. 731-740, Apr. 2010.
[2] Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu and Ying-Zu Lin, "10-bit 30-MS/s SAR ADC Using a Switchback Switching Method," IEEE Transactions on VLSI Systems, vol. 21, no. 3, pp.584-588, Mar. 2013. (SCI, EI)
[3] Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu and Guan-Ying Huang, "An Asynchronous Binary-Search ADC Architecture with a Reduced Comparator Count," IEEE Transactions on Circuits and Systems - I, vol. 57, no. 8, pp.1829-1837, Aug. 2010. (SCI, EI)
[4] Hariprasath, V., Guerber, J., Lee, S.-H., and Moon, U.-K. “Merged capacitor switching based SAR ADC with highest switching energy efficiency,” Electron. Lett., 2010,46,(9), pp. 620-621.
[5] C.Yuan and Y.Lam., “Low-energy and area-efficient tri-level switching scheme for SAR ADC,” Electron. Lett., 2012,48,(9), pp. 482-483.
[6] G.-Y. Huang, C.-C. Liu, Y.-Z. Lin, and S.-J. Chang, “A 10-bit 12 MS/ssuccessive approximation ADC with 1.2-pF input capacitance,” in IEEE ASSCC Dig. Tech. Papers, Nov. 2009, pp. 157–160.
[7] Sang-Pil Nam, Yong-Min Kim, Dong-Hyun Hwang, Hyo-Jin Kim, Tai-Ji An, Jun-Sang Park, Suk-Hee Cho, Gil Cho Ahn and Seung-Hoon Lee, “A 10-bit 1 MS/s-to-10MS/s 0.11um CMOS SAR ADC for Analog TV Applications,” international Soc Design Conference (ISOCC), pp.142-147, Nov.4-7,2012.
[8] Allen, P.E., and Holberg, D.R.: ‘CMOS Analog Circuit Design’ (Oxford University Press, Inc., New York, USA, 2002, 2nd Edn.)
[9] Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto and T. Kuroda,“Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC,” CICC, pp. 279-282, Sep. 2009.
[10] Ting Yang, Li Zhiqun, “A 7-bit 26-MS/s SAR ADC in 0.18um CMOS process for WSN application,” High speed Intelligent Communication Forum(HSIC), 2012 4th international, pp.1-4, May. 2012.
[11] Zhuang Zhaodong, Li Zhiqun, "A 7-bit 16-MS/s low-power CMOS pipeline ADC," Communication Technology (ICCT), 2011 IEEE 13th international Conference, pp.1082-1085, Sept. 2011.

全文公開日期 2019/07/17 (校內網路)
全文公開日期本全文未授權公開 (校外網路)
全文公開日期本全文未授權公開 (國家圖書館：臺灣博碩士論文系統)

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