簡易檢索 / 詳目顯示

研究生: 高培修
Pei-Hsiu Kao
論文名稱: 雜訊整形連續漸進式類比數位轉換器與電容不匹配削減技術之設計與實現
Design and Implementation of Noise-Shaping SAR ADCs with Capacitor Mismatch Reduction Schemes
指導教授: 鍾勇輝
Yung-Hui Chung
口試委員: 陳信樹
Hsin-Shu Chen
陳伯奇
Poki Chen
陳筱青
Hsiao-Chin Chen
鍾勇輝
Yung-Hui Chung
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2023
畢業學年度: 111
語文別: 中文
論文頁數: 90
中文關鍵詞: 雜訊整形連續漸進式類比數位轉換器電容交換快速視窗切換
外文關鍵詞: Noise-Shaping, SAR ADC, Capacitor Swapping, Fast Binary Window
相關次數: 點閱:220下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 本論文探討雜訊整形連續漸進式類比數位轉換器的設計與應用。在本論文中,分別設計了兩顆晶片,使用不同的電路技巧來達成雜訊整形,並加入了電容交換(Capacitor Swapping)和快速視窗切換技術(Fast Binary Window)來增加電容式數位類比轉換器線性度。
    在UMC 180奈米製程下,第一顆晶片使用誤差回授的方式來達到雜訊整形的效果。其取樣頻率為8 MHz、OSR為8。在供應電壓為1.8伏特的情況下,功耗為1.18毫瓦。量測到的有效位元(ENOB)為10.73 bits、無雜散動態範圍(Spurious-Free Dynamic Range, SFDR)為71.85 dB、訊號雜訊比(Signal to Noise Ratio, SNR)為67.21 dB。
    第二顆晶片使用積分器來構建整體架構。在TSMC 90奈米製程下,取樣頻率為4 MHz、OSR為16、供應電壓為1.2伏特的後模擬功耗為0.46毫瓦。後模擬結果得到的有效位元為14.9 bits、無雜散動態範圍為101.3 dB、訊號雜訊比為91.7 dB,等效的FOMs為175.6 dB。


    This thesis explores the design and application of two noise-shaping successive-approximation-register (SAR) analog-to-digital converters (ADCs). In this thesis, two chips are designed respectively, using different circuit techniques to achieve noise shaping. Moreover, adding capacitor swapping and fast window switching schemes to increase the linearity of capacitive digital-to-analog converter (DAC).
    Fabricated in UMC 180 nm process, the first chip uses error feedback to achieve the effect of noise shaping. Its sampling frequency is 8 MHz and its oversampling ratio (OSR) is 8. With a supply voltage of 1.8 volts, its power dissipation is 1.18 milliwatts. The measured effective number of bits (ENOB) is 10.73 bits, the spurious-free dynamic range (SFDR) is 71.85 dB, and the signal-to-noise ratio (SNR) is 67.21 dB.
    The second chip utilizes an integrator-based architecture to achieve the effect of noise shaping. Fabricated in the TSMC 90 nm CMOS process, with a sampling frequency of 4 MHz, an OSR of 16, and a supply voltage of 1.2 volts, the simulated power consumption is 0.46 milliwatts. The post-layout simulation results yield an ENOB of 14.9 bits, an SFDR of 101.3 dB, and an SNR of 91.7 dB, which is equivalent to a FOMs of 175.6 dB.

    論文摘要 ..................................................................................................... I Abstract .................................................................................................... II 誌謝 .......................................................................................................... III 目錄 .......................................................................................................... IV 表格目錄 ................................................................................................. VII 圖目錄 ................................................................................................... VIII 第一章 序論............................................................................................... 1 1-1. 研究動機 ............................................................................................................ 1 1-2. 章節介紹 ............................................................................................................ 1 第二章 類比數位轉換器技術 .................................................................. 3 2-1. 奈奎斯特理論 .................................................................................................... 3 2-2. 過取樣理論 ........................................................................................................ 4 2-3. 雜訊整形 ............................................................................................................ 5 第三章 雜訊整形類比數位轉換器 .......................................................... 8 3-1. 連續漸近式類比數位轉換器 ............................................................................ 8 3-2. 三角積分調變器 ................................................................................................ 9 3-3. 雜訊整形連續漸近式類比數位轉換器 .......................................................... 10 3-3-1 誤差回授 ................................................................................................... 10 3-3-2 前饋型串接積分器 ................................................................................... 12 第四章 誤差回授連續漸進式類比數位轉換器 .................................... 16 4-1. MATLAB分析 ............................................................................................... 16 4-1-1 係數分析 ................................................................................................... 17 4-1-2 係數偏移 ................................................................................................... 19 4-1-3 雜訊分析 ................................................................................................... 20 4-2. 九位元連續漸近式類比數位轉換器 .............................................................. 23 4-2-1 取樣保持電路 ........................................................................................... 23 4-2-2 動態比較器 ............................................................................................... 25 4-2-3 電容陣列 ................................................................................................... 28 4-2-4 二進制快速視窗切換技術 ....................................................................... 29 4-2-5 一階電容交換技術 ................................................................................... 31 4-3. 有限脈衝響應濾波器 ...................................................................................... 34 4-3-1 殘值放大器 ............................................................................................... 34 4-3-2 開關電容電路 ........................................................................................... 37 4-4. 電路佈局圖 ...................................................................................................... 39 4-5. 模擬結果 .......................................................................................................... 42 4-6. 量測結果 .......................................................................................................... 42 第五章 前饋型串接積分連續漸近式類比數位轉換器 ........................ 47 5-1 Matlab分析 .................................................................................................... 49 5-1-1 係數分析 ................................................................................................... 50 5-1-2 雜訊分析 ................................................................................................... 50 5-2 九位元連續漸近式類比數位轉換器 .............................................................. 51 5-2-1 取樣電路 ................................................................................................... 52 5-2-2 電容陣列 ................................................................................................... 52 5-2-3 三位元快速視窗切換技術 ....................................................................... 53 5-2-4 二階電容交換技術 ................................................................................... 54 5-3 電容串接加法器 .............................................................................................. 56 5-3-1 電容串接操作 ........................................................................................... 57 5-3-2 電容串接寄生影響 ................................................................................... 58 5-4 積分器 .............................................................................................................. 62 5-4-1 浮動反向式放大器 (Floating Inverting Amplifier) ............................. 63 5-4-2 串接式浮動反向式放大器 ....................................................................... 64 5-4-3 快速穩定機制 ........................................................................................... 65 5-5 電路佈局 .......................................................................................................... 66 5-6 模擬結果 .......................................................................................................... 68 第六章 結論與未來展望 ........................................................................ 71 6-1. 結論 .................................................................................................................. 71 6-2. 未來展望 .......................................................................................................... 71 參考文獻 ................................................................................................... 73

    [1] L. Jie et al., "An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 149-161, 2021, doi: 10.1109/OJSSCS.2021.3119910.
    [2] M. -H. Wu, Y. -H. Chung and H. -S. Li, "A 12-bit 8.47-fJ/conversion-step 1-MS/s SAR ADC using capacitor-swapping technique," 2012 IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, Japan, 2012, pp. 157-160, doi: 10.1109/IPEC.2012.6522649.
    [3] Y. -H. Chung, Y. -S. Lin and Q. -F. Zeng, "A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS," 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Chengdu, China, 2018, pp. 34-37, doi: 10.1109/APCCAS.2018.8605686.
    [4] Y. -H. Chung, C. -H. Tien and Q. -F. Zeng, "A 16-Bit Calibration-Free SAR ADC With Binary-Window and Capacitor-Swapping DAC Switching Schemes," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 1, pp. 88-99, Jan. 2022, doi: 10.1109/TCSI.2021.3096242.
    [5] R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters Piscataway, NJ, USA: Wiley, 2005.
    [6] B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, "Yield and speed optimization of a latch-type voltage sense amplifier," in IEEE Journal of Solid-State Circuits, vol.

    39, no. 7, pp. 1148-1158, July 2004, doi: 10.1109/JSSC.2004.829399.
    [7] Y. -H. Chung, C. -W. Yen and C. -H Tsai, 'A 12-bit 1-MS/s 26-μW SAR ADC for Sensor Applications," 2016 Physical Sciences Reviews
    [8] Y. -H. Chung, Y. -S. Lin and Q. -F. Zeng, "A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS," 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Chengdu, China, 2018, pp. 34-37, doi: 10.1109/APCCAS.2018.8605686.
    [9] X. Tang et al., "An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier," in IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1011-1022, April 2020, doi: 10.1109/JSSC.2019.2960485.
    [10] S. Li, B. Qiao, M. Gandara, D. Z. Pan and N. Sun, "A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure," in IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3484-3496, Dec. 2018, doi: 10.1109/JSSC.2018.2871081.
    [11] H. Zhuang et al., "A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting," in IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1636-1647, June 2019, doi: 10.1109/JSSC.2019.2900150.
    [12] W. Guo and N. Sun, "A 12b-ENOB 61μW noise-shaping SAR ADC with a passive integrator," ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 2016, pp. 405-408, doi:
    10.1109/ESSCIRC.2016.7598327.
    [13] Y. -Z. Lin, C. -Y. Lin, S. -C. Tsou, C. -H. Tsai and C. -H. Lu, "20.2 A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 330-332, doi: 10.1109/ISSCC.2019.8662299.
    [14] R. S. A. Kumar, N. Krishnapura and P. Banerjee, "Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier," in IEEE Journal of Solid-State Circuits, vol. 57, no. 11, pp. 3384-3395, Nov. 2022, doi: 10.1109/JSSC.2022.3171790.
    [15] X. Tang, X. Yang, J. Liu, W. Shi, D. Z. Pan and N. Sun, "27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier," 2021 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021, pp. 376-378, doi: 10.1109/ISSCC42613.2021.9365753.
    [16] X. Tang et al., "A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier," in IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3248-3259, Dec. 2020, doi: 10.1109/JSSC.2020.3020194.
    [17] H. . -S. Lee, D. A. Hodges and P. R. Gray, "A self-calibrating 15 bit CMOS A/D converter," in IEEE Journal of Solid-State Circuits, vol. 19, no. 6, pp. 813-819, Dec. 1984, doi: 10.1109/JSSC.1984.1052231.
    [18] W. -H. Tseng, W. -L. Lee, C. -Y. Huang and P. -C. Chiu, "A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters," in IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2222-2231, Oct. 2016, doi: 10.1109/JSSC.2016.2582861.

    無法下載圖示 全文公開日期 2025/08/08 (校內網路)
    全文公開日期 2028/08/08 (校外網路)
    全文公開日期 2028/08/08 (國家圖書館:臺灣博碩士論文系統)
    QR CODE