是貼近於我們的生活。這之中，如何使產品能達到越高的解析度、低功耗，且高線性度，甚至能運用至更廣泛的訊號頻寬，都是類比/數位轉換器其具挑戰性的研究目標。
本篇論文設計一個可用於寬信號頻帶和高動態範圍的連續型三角積分調變器，藉由超取樣及多級雜訊移頻來有效的抑制量化雜訊，Discrete-time (DT)∆Sturdy-MASH的架構受到取樣頻率的限制，所以在此以Continuous-time (CT) ∆Sturdy-MASH的架構實現，在連續型三角積分調變器中可以應用於較寬的信號頻帶。連續型三角積分調變器在設計挑戰上，有如何使系統穩定收斂和額外迴路延遲等問題，在此將以Hybrid SMASH(HSMASH)的架構來實現，其中以全差動OTA來完成整個系統，進一步實現三階的HSMASH-21。晶片使用TSMC 90 nm製程，晶片面積〖1.376 mm〗^2，操作電壓1.2 V，取樣頻率640MHz，OSR為32；系統頻寬10 MHz，解析度達到8.02 bit，功率消耗為16.4mW。

Analog to Digital converter ADC is widely used in the gadget of our daily lives. To make the ADC achieve high resolution, low power consumption, high linearity, and can be applicable to wide bandwidth signals, are challenging.
This thesis designs a continuous-time (CT) delta-sigma modulator DSM that can be used for wide signal bandwidth and high dynamic range. It uses oversampling and multi-level noise shaping to suppress quantization noise effectively. The bandwidth of signal for a discrete-time (DT) Sturdy-MASH (SMASH) modulator is limited by the sampling frequency, so we adopt the CT Sturdy-MASH architecture that can be applied for a signal with bandwidth. The DSM of this work was implemented with the third order hybrid-SMASH (HSMASH) 21 architecture, in which the entire system is realized in fully-differential amplifiers. The chip is designed in the TSMC 90 nm CMOS process. The chip area is〖 1.376 mm〗^2, the operating voltage is 1.2 V, the sampling frequency is 640 MHz, the OSR is 32 and the system bandwidth is 10 MHz .The best resolution can reache 8.02 bits, and the power consumption is 16.4 mW .

[1] Chauchin Su; Po-Chen Lin; Hungwen Lu ,” An Inverter Based 2-MHz 42μW ΔΣ ADC with 20-KHz Bandwidth and 66dB Dynamic Range” , IEEE Asian Solid-State Circuits Conference, May 2006, pp. 63-66.
[2] Chae, Youngcheol, and Gunhee Han. "Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator." IEEE Journal of Solid-State Circuits 44.2 (2009): 458-472.
[3] Liu, Szu-Chieh, and Kea-Tiong Tang. "A low-voltage low-power sigma-delta modulator for bio-potential signals." 2011 IEEE/NIH Life Science Systems and Applications Workshop (LiSSA). IEEE, 2011.
[4] Michel, Fridolin, and Michiel SJ Steyaert. "A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ modulator using near-threshold-voltage-biased inverter amplifiers in 130 nm CMOS." IEEE Journal of solid-state circuits 47.3 (2012): 709-721.
[5] De la Rosa, José M., et al. "A CMOS 110-dB@ 40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta modulator for low-power high-linearity automotive sensor ASICs." IEEE Journal of Solid-State Circuits 40.11 (2005): 2246-2264.
[6] 黃濬杰，「低功耗之二階強健式多級三角積分類比數位轉換器｣ ，國立台灣科技大學電機工程學系碩士論文，中華名國一百零二年一月。
[7] 游仲祥，「低功耗之改良強健式MASH-21三角積分類比數位轉換器｣ ，國立台灣科技大學電機工程學系碩士論文，中華名國一百零四年一月。
[8] 劉育勳，「低功耗等效13.5位元之改良強健式MASH-21三角積分類比數位轉換器｣ ，國立台灣科技大學電機工程學系碩士論文，中華名國一百零六年一月。
[9] 張庭卉，「音訊應用等效11.75位元之改良強健式MASH-21三角積分類比數位展和器｣ ，國立台灣科技大學電機工程學系碩士論文，中華名國一百零八年四月。
[10] D. Yoon, S. Ho and H. Lee, "A Continuous-Time Sturdy-MASH sigma-delta Modulator in 28 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2880-2890, Dec. 2015, doi: 10.1109/JSSC.2015.2466459.
[11] S. Yan and E. Sanchez-Sinencio, "A continuous-time sigma-delta modulator with 88dB dynamic range and 1.1MHz signal bandwidth," 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., San Francisco, CA, USA, 2003, pp. 62-478 vol.1, doi: 10.1109/ISSCC.2003.1234208.
[12] H. Kim, J. Lee, T. Copani, S. Bazarjani, S. Kiaei and B. Bakkaloglu, "Adaptive blocker rejection continuous-time sigma-delta ADC for mobile wimax applications," in IEEE Journal of Solid-State Circuits, vol. 44, no. 10, pp. 2766-2779, Oct. 2009, doi: 10.1109/ JSSC. 2009. 2028053.
[13] Y. Shu, B. Song and K. Bacrania, "A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, 2008, pp. 500-631, doi: 10.1109/ ISSCC. 2008. 4523276.
[14] M. Park and M. H. Perrott, "A 78dB SNDR 87mW 20 MHz bandwidth continuous-time sigma-delta ADC With VCO-Based Integrator and Quantizer Implemented in 0.13mm CMOS," in IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3344-3358, Dec. 2009, doi: 10.1109/JSSC.2009.2032703.
[15] M. Ortmanns, F. Gerfers and Y. Manoli, "A case study on a 2-1-1 cascaded continuous-time sigma-delta Modulator," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 8, pp. 1515-1525, Aug. 2005, doi: 10.1109/TCSI.2005.852024.

[16] H. Shamsi and O. Shoaei, "A novel structure for the design of 2-1-1 cascaded continuous time delta sigma modulators," 2006 IEEE International Symposium on Circuits and Systems, Island of Kos, 2006, pp. 4 pp.-, doi: 10.1109/ISCAS.2006.1693692.
[17] R. Tortosa, J. M. de la Rosa, A. Rodriguez-Vazquez and F. V. Fernandez, "A direct synthesis method of cascaded continuous-time sigma-delta modulators," 2005 IEEE International Symposium on Circuits and Systems, Kobe, 2005, pp. 5585-5588 Vol. 6, doi: 10.1109/ISCAS.2005.1465903.
[18] R. Tortosa, J. M. De La Rosa, F. V. Fernandez and A. Rodriguez-Vazquez, "A new high-level synthesis methodology of cascaded continuous-time sigma-delta modulators," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 8, pp. 739-743, Aug. 2006, doi: 10.1109/TCSII.2006.875310.
[19] D. Y. Yoon, H. Lee and J. Gealow, "Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators," 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, 2013, pp. 562-565, doi: 10.1109/MWSCAS.2013.6674710.
[20] 趙家祥，「X 頻帶 9.75/10.6 GHz 頻率合成器的設計與實現｣ ，國立台灣師範大學應用電子科技學系碩士論文，中華名國一百零三年七月。
[21] J. A. Cherry and W. M. Snelgrove, "Excess loop delay in continuous-time delta-sigma modulators," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 4, pp. 376-389, April 1999, doi: 10.1109/82.755409.
[22] 紀壬弘，「一個應用於多位元連續時間三角積分調變器的新穎電流式數位類比轉換器校正紀數｣ ，國立中正大學電機工程研究所碩士論文，中華名國九十九年一月。
[23] 王大瑋，「適用於寬頻通訊系統使用預測架構之連續時間三角積分調變器｣ ，國立中正大學電機工程研究所碩士論文，中華名國一百零一年十月。

[24] M. Bolatkale, L. J. Breems, R. Rutten and K. A. A. Makinwa, "A 4GHz CT ΔΣ ADC with 70dB DR and −74dBFS THD in 125MHz BW," 2011 IEEE International Solid-State Circuits Conference, San Francisco, CA, 2011, pp. 470-472, doi: 10.1109/ISSCC.2011.5746401.
[25] G. Mitteregger et al., "A 14b 20mW 640MHz CMOS CT delta-sigma ADC with 20MHz Signal Bandwidth and 12b ENOB," 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, San Francisco, CA, 2006, pp. 131-140, doi: 10.1109/ISSCC.2006.1696042.
[26] J. Huang, S. Yang and J. Yuan, "A 10-MHz bandwidth 70-dB SNDR 640MS/s continuous-time ΣΔ ADC using Gm-C filter with nonlinear feedback DAC calibration," Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, 2013, pp. 1-4, doi: 10.1109/CICC.2013.6658458.
[27] L. Qi, A. Jain, D. Jiang, S. Sin, R. P. Martins and M. Ortmanns, "A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance," in IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 344-355, Feb. 2020, doi: 10.1109/JSSC.2019.2942359.