快閃記憶體為重要且常見的儲存裝置之一，因科技快速進步和資訊量增長，快閃記憶體的需求也隨之上升。快閃記憶體為非揮發性記憶體，具有低功耗、低成本、高儲存容量和可擴展性等特性，使它成為各種電子產品中必要的裝置。然而快閃記憶體具有耐久度的問題，其可靠度會隨著寫入及抹除次數、讀取次數和資料保留時間等因素而下降。隨著製程的微縮，這些問題變得更加嚴重且需要被重視。
BCH 碼為常被使用於快閃記憶體的錯誤更正碼之一，他可以一次保護多個位元的資料，然而需要較長的解碼延遲，解碼延遲也會隨著保護能力增強而提高。因此我們使用漸進式錯誤更正碼技術，在快閃記憶體上配置多個保護階層。再藉由分析解碼時編碼字的修正餘度來決定是否要將配置於記憶體頁的保護階層升級。因為升級過後的編碼字會產生額外的檢查位元，我們將額外檢查位元存在靜態隨機存取記憶體內再使用內容可定址記憶體紀錄。另外，本篇論文藉由模擬快閃記憶體在不同位元錯誤率下的保護能力使用情況來找出一組保護能力組合，此組合可以用來最佳化快閃記憶體生命週期下的平均解碼時間。
另外，本篇研究將解碼流程分為錯誤偵測以及錯誤更正兩階段。若偵測出編碼字有發生錯誤時再進行後續的錯誤更正流程，可以減少沒有發生錯誤的編碼字之解碼時間。在編解碼的硬體架構方面，我們使用可重組式 BCH 碼之編解碼器，藉由使用一組 BCH 碼編解碼電路即可以做多種保護能力的編解碼。
我們進行可靠度、良率、效能等分析，並實現了低延遲及錯誤曉知之漸進式錯誤更正碼技術之電路。相較於使用單一保護能力的錯誤更正碼，我們使用的低延遲及錯誤曉知之漸進式錯誤更正碼技術最多可以減少 87.5% 的平均解碼延遲，並且在記憶體操作 9×10^5 小時後仍可以維持達 0.998 的可靠度。

Flash memory is one of the important storage devices which is widely used in our daily lives. The demand of flash memories grows with the rapid advance of technology and the information explosion. Flash memory is a type of nonvolatile memory and features low power, low cost, large storage capacity, and scalability. However, flash memory suffers from the reliability and limited endurance issues. The reliability of a flash cell is affected by program and erase cycles, read disturbance, and data retention time. As the process scaling down, the endurance and reliability issues become more serious.
BCH code is a kind of error correction codes which is widely adopted for flash memory for data repair. BCH code can correct multiple errors though the decoding process requires long latency. Moreover, the required latency rises as the ECC protection capacity increases. Therefore, we propose a progressive ECC technique, which includes multiple ECC protection levels to be applied to flash memory. We decide whether the protection levels of flash memory pages should be upgraded through analyzing the correction slack of codewords during decoding. Since the codewords encoded with a higher protection level include more check bits as compared to codewords protected by the default level, we store the extra check bits in SRAM and record the physical page numbers on content addressable memory. Furthermore, we simulate the utilization of ECC protection capacities under different RBER to find a ECC protection capacity combination which can lower the average decoding latency throughout the lifetime of flash memory.
Furthermore, our thesis separates the decoding process into error detection and error correction phases. Error correction is required only if the codeword is erroneous. This method reduces the decoding latency of error-free codewords. Besides, we use a reconfigurable BCH codec in our design, which can perform encoding and decoding for multiple BCH protection levels.
We analyze the reliability, yield, performance and implement the architecture of the proposed method. Compared with using a uniform ECC protection capacity, the proposed progressive ECC technique reduces the decoding latency up to 87.5% and maintains the reliability at 0.998 after 9×10^5 operation hours.

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